[ros-diffs] [ros-arm-bringup] 32318: We now define the cache and id registers in CP15 (C0 Opcode 0 and 1). We now setup ARM cache information in the loader block. We now allocate the kernel, interrupt and abort stacks, as well as the idle thread and process, and boot PRCB. We now allocate the PCR and PDR pages. We now send the command line to the kernel in the LoaderBlock's load options.
ros-arm-bringup at svn.reactos.org
ros-arm-bringup at svn.reactos.org
Tue Feb 12 10:41:21 CET 2008
Author: ros-arm-bringup
Date: Tue Feb 12 12:41:21 2008
New Revision: 32318
URL: http://svn.reactos.org/svn/reactos?rev=32318&view=rev
Log:
We now define the cache and id registers in CP15 (C0 Opcode 0 and 1).
We now setup ARM cache information in the loader block.
We now allocate the kernel, interrupt and abort stacks, as well as the idle thread and process, and boot PRCB.
We now allocate the PCR and PDR pages.
We now send the command line to the kernel in the LoaderBlock's load options.
Modified:
trunk/reactos/boot/freeldr/freeldr/arch/arm/loader.c
trunk/reactos/ntoskrnl/include/internal/arm/intrin_i.h
trunk/reactos/ntoskrnl/include/internal/arm/ke.h
Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/loader.c
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/arch/arm/loader.c?rev=32318&r1=32317&r2=32318&view=diff
==============================================================================
--- trunk/reactos/boot/freeldr/freeldr/arch/arm/loader.c (original)
+++ trunk/reactos/boot/freeldr/freeldr/arch/arm/loader.c Tue Feb 12 12:41:21 2008
@@ -20,6 +20,32 @@
LOADER_PARAMETER_EXTENSION ArmExtension;
extern ARM_TRANSLATION_TABLE ArmTranslationTable;
extern ROS_KERNEL_ENTRY_POINT KernelEntryPoint;
+
+ULONG SizeBits[] =
+{
+ -1, // INVALID
+ -1, // INVALID
+ 1 << 12, // 4KB
+ 1 << 13, // 8KB
+ 1 << 14, // 16KB
+ 1 << 15, // 32KB
+ 1 << 16, // 64KB
+ 1 << 17 // 128KB
+};
+
+ULONG AssocBits[] =
+{
+ -1, // INVALID
+ -1, // INVALID
+ 4 // 4-way associative
+};
+
+ULONG LenBits[] =
+{
+ -1, // INVALID
+ -1, // INVALID
+ 8 // 8 words per line (32 bytes)
+};
/* FUNCTIONS ******************************************************************/
@@ -115,6 +141,9 @@
VOID
ArmPrepareForReactOS(IN BOOLEAN Setup)
{
+ ARM_CACHE_REGISTER CacheReg;
+ PVOID Base;
+
//
// Initialize the loader block
//
@@ -153,8 +182,63 @@
//
//
- // TODO: Setup ARM-specific block
- //
+ // Send the command line
+ //
+ ArmLoaderBlock.LoadOptions = reactos_kernel_cmdline;
+
+ //
+ // Setup cache information
+ //
+ CacheReg = KeArmCacheRegisterGet();
+ ArmLoaderBlock.u.Arm.FirstLevelDcacheSize = SizeBits[CacheReg.DSize];
+ ArmLoaderBlock.u.Arm.FirstLevelDcacheFillSize = LenBits[CacheReg.DLength];
+ ArmLoaderBlock.u.Arm.FirstLevelDcacheFillSize <<= 2;
+ ArmLoaderBlock.u.Arm.FirstLevelIcacheSize = SizeBits[CacheReg.ISize];
+ ArmLoaderBlock.u.Arm.FirstLevelIcacheFillSize = LenBits[CacheReg.ILength];
+ ArmLoaderBlock.u.Arm.FirstLevelIcacheFillSize <<= 2;
+ ArmLoaderBlock.u.Arm.SecondLevelDcacheSize =
+ ArmLoaderBlock.u.Arm.SecondLevelDcacheFillSize =
+ ArmLoaderBlock.u.Arm.SecondLevelIcacheSize =
+ ArmLoaderBlock.u.Arm.SecondLevelIcacheFillSize = 0;
+
+ //
+ // Allocate the Interrupt stack
+ //
+ Base = MmAllocateMemoryWithType(KERNEL_STACK_SIZE, LoaderStartupDpcStack);
+ ArmLoaderBlock.u.Arm.InterruptStack = KSEG0_BASE | (ULONG)Base;
+
+ //
+ // Allocate the Kernel Boot stack
+ //
+ Base = MmAllocateMemoryWithType(KERNEL_STACK_SIZE, LoaderStartupKernelStack);
+ ArmLoaderBlock.KernelStack = KSEG0_BASE | (ULONG)Base;
+
+ //
+ // Allocate the Abort stack
+ //
+ Base = MmAllocateMemoryWithType(KERNEL_STACK_SIZE, LoaderStartupPanicStack);
+ ArmLoaderBlock.u.Arm.PanicStack = KSEG0_BASE | (ULONG)Base;
+
+ //
+ // Allocate the PCRs (1MB each for now!)
+ //
+ Base = MmAllocateMemoryWithType(2 * 1024 * 1024, LoaderStartupPcrPage);
+ ArmLoaderBlock.u.Arm.PcrPage = (ULONG)Base >> TTB_SHIFT;
+ ArmLoaderBlock.u.Arm.PcrPage2 = ArmLoaderBlock.u.Arm.PcrPage + 1;
+
+ //
+ // Allocate PDR pages
+ //
+ Base = MmAllocateMemoryWithType(3 * 1024 * 1024, LoaderStartupPdrPage);
+ ArmLoaderBlock.u.Arm.PdrPage = (ULONG)Base >> TTB_SHIFT;
+
+ //
+ // Set initial PRCB, Thread and Process on the last PDR page
+ //
+ Base = (PVOID)((ULONG)Base + 2 * 1024 * 1024);
+ ArmLoaderBlock.Prcb = KSEG0_BASE | (ULONG)Base;
+ ArmLoaderBlock.Process = ArmLoaderBlock.Prcb + sizeof(KPRCB);
+ ArmLoaderBlock.Thread = ArmLoaderBlock.Process + sizeof(EPROCESS);
}
VOID
@@ -176,5 +260,6 @@
//
// Initialize paging and load NTOSKRNL
//
+ TuiPrintf("Kernel Command Line: %s\n", ArmLoaderBlock.LoadOptions);
ArmSetupPagingAndJump(Magic);
}
Modified: trunk/reactos/ntoskrnl/include/internal/arm/intrin_i.h
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/include/internal/arm/intrin_i.h?rev=32318&r1=32317&r2=32318&view=diff
==============================================================================
--- trunk/reactos/ntoskrnl/include/internal/arm/intrin_i.h (original)
+++ trunk/reactos/ntoskrnl/include/internal/arm/intrin_i.h Tue Feb 12 12:41:21 2008
@@ -21,6 +21,26 @@
}
FORCEINLINE
+ARM_ID_CODE_REGISTER
+KeArmIdCodeRegisterGet(VOID)
+{
+ ARM_ID_CODE_REGISTER Value;
+ __asm__ __volatile__ ("mrc p15, 0, %0, c0, c0, 0" : "=r"(Value.AsUlong) : : "cc");
+ return Value;
+}
+
+
+FORCEINLINE
+ARM_CACHE_REGISTER
+KeArmCacheRegisterGet(VOID)
+{
+ ARM_CACHE_REGISTER Value;
+ __asm__ __volatile__ ("mrc p15, 0, %0, c0, c0, 1" : "=r"(Value.AsUlong) : : "cc");
+ return Value;
+}
+
+
+FORCEINLINE
VOID
KeArmControlRegisterSet(IN ARM_CONTROL_REGISTER ControlRegister)
{
Modified: trunk/reactos/ntoskrnl/include/internal/arm/ke.h
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/include/internal/arm/ke.h?rev=32318&r1=32317&r2=32318&view=diff
==============================================================================
--- trunk/reactos/ntoskrnl/include/internal/arm/ke.h (original)
+++ trunk/reactos/ntoskrnl/include/internal/arm/ke.h Tue Feb 12 12:41:21 2008
@@ -65,6 +65,40 @@
ULONG AsUlong;
} ARM_CONTROL_REGISTER, *PARM_CONTROL_REGISTER;
+typedef union _ARM_ID_CODE_REGISTER
+{
+ struct
+ {
+ ULONG Revision:4;
+ ULONG PartNumber:12;
+ ULONG Architecture:4;
+ ULONG Variant:4;
+ ULONG Identifier:8;
+ };
+ ULONG AsUlong;
+} ARM_ID_CODE_REGISTER, *PARM_ID_CODE_REGISTER;
+
+typedef union _ARM_CACHE_REGISTER
+{
+ struct
+ {
+ ULONG ILength:2;
+ ULONG IMultipler:1;
+ ULONG IAssociativty:3;
+ ULONG ISize:4;
+ ULONG IReserved:2;
+ ULONG DLength:2;
+ ULONG DMultipler:1;
+ ULONG DAssociativty:3;
+ ULONG DSize:4;
+ ULONG DReserved:2;
+ ULONG Separate:1;
+ ULONG CType:4;
+ ULONG Reserved:3;
+ };
+ ULONG AsUlong;
+} ARM_CACHE_REGISTER, *PARM_CACHE_REGISTER;
+
typedef enum _ARM_DOMAINS
{
Domain0,
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