[ros-diffs] [fireball] 27787: - Add an OLPC-specific pci-hack: some of its "PCI" devices are in fact not accessible via usual pci configuration space read/write mechanism, so a simulation should be done. The olpcpci.c file is taken from OLPC's dev.laptop.org tree, and modified by me. - USB driver now finds the EHCI controller, but still some problems.
fireball at svn.reactos.org
fireball at svn.reactos.org
Mon Jul 23 15:43:57 CEST 2007
Author: fireball
Date: Mon Jul 23 17:43:57 2007
New Revision: 27787
URL: http://svn.reactos.org/svn/reactos?rev=27787&view=rev
Log:
- Add an OLPC-specific pci-hack: some of its "PCI" devices are in fact not accessible via usual pci configuration space read/write mechanism, so a simulation should be done. The olpcpci.c file is taken from OLPC's dev.laptop.org tree, and modified by me.
- USB driver now finds the EHCI controller, but still some problems.
Added:
branches/olpc/hal/halx86/generic/olpcpci.c (with props)
Modified:
branches/olpc/hal/halx86/generic/generic.rbuild
branches/olpc/hal/halx86/generic/pci.c
Modified: branches/olpc/hal/halx86/generic/generic.rbuild
URL: http://svn.reactos.org/svn/reactos/branches/olpc/hal/halx86/generic/generic.rbuild?rev=27787&r1=27786&r2=27787&view=diff
==============================================================================
--- branches/olpc/hal/halx86/generic/generic.rbuild (original)
+++ branches/olpc/hal/halx86/generic/generic.rbuild Mon Jul 23 17:43:57 2007
@@ -10,6 +10,7 @@
<file>dma.c</file>
<file>drive.c</file>
<file>misc.c</file>
+ <file>olpcpci.c</file>
<file>pci.c</file>
<file>portio.c</file>
<file>profil.c</file>
Added: branches/olpc/hal/halx86/generic/olpcpci.c
URL: http://svn.reactos.org/svn/reactos/branches/olpc/hal/halx86/generic/olpcpci.c?rev=27787&view=auto
==============================================================================
--- branches/olpc/hal/halx86/generic/olpcpci.c (added)
+++ branches/olpc/hal/halx86/generic/olpcpci.c Mon Jul 23 17:43:57 2007
@@ -1,0 +1,294 @@
+/*
+ * olpcpci.c - Low-level PCI config space access for OLPC systems
+ * without the VSA PCI virtualization software.
+ *
+ * The AMD Geode chipset (GX2 processor, cs5536 I/O companion device)
+ * has some I/O functions (display, southbridge, sound, USB HCIs, etc)
+ * that more or less behave like PCI devices, but the hardware doesn't
+ * directly implement the PCI configuration space headers. AMD provides
+ * "VSA" (Virtual System Architecture) software that emulates PCI config
+ * space for these devices, by trapping I/O accesses to PCI config register
+ * (CF8/CFC) and running some code in System Management Mode interrupt state.
+ * On the OLPC platform, we don't want to use that VSA code because
+ * (a) it slows down suspend/resume, and (b) recompiling it requires special
+ * compilers that are hard to get. So instead of letting the complex VSA
+ * code simulate the PCI config registers for the on-chip devices, we
+ * just simulate them the easy way, by inserting the code into the
+ * pci_write_config and pci_read_config path. Most of the config registers
+ * are read-only anyway, so the bulk of the simulation is just table lookup.
+ */
+
+//#include <linux/pci.h>
+//#include <linux/init.h>
+//#include <asm/olpc.h>
+//#include <asm/geode.h>
+//#include "pci.h"
+
+/* INCLUDES ******************************************************************/
+
+#include <hal.h>
+#define NDEBUG
+#include <debug.h>
+
+/* GLOBALS *******************************************************************/
+
+static int is_lx = FALSE; //FIXME: Support LX too!
+
+#define PCI_SLOT(dev, fn) ((((fn) & 0x7) << 5) | ((dev) & 0x1F))
+
+/*
+ * In the tables below, the first two line (8 longwords) are the
+ * size masks that are used when the higher level PCI code determines
+ * the size of the region by writing ~0 to a base address register
+ * and reading back the result.
+ *
+ * The following lines are the values that are read during normal
+ * PCI config access cycles, i.e. not after just having written
+ * ~0 to a base address register.
+ */
+
+static const ULONG lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x281022 , 0x2200005 , 0x6000021 , 0x80f808 , /* AMD Vendor ID */
+ 0x0 , 0x0 , 0x0 , 0x0 , /* No virtual registers, hence no BAR for them */
+ 0x0 , 0x0 , 0x0 , 0x28100b ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+static const ULONG gxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
+ 0xfffffffd , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x28100b , 0x2200005 , 0x6000021 , 0x80f808 , /* NSC Vendor ID */
+ 0xac1d , 0x0 , 0x0 , 0x0 , /* I/O BAR - base of virtual registers */
+ 0x0 , 0x0 , 0x0 , 0x28100b ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+static const ULONG lxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */
+ 0xff800008 , 0xffffc000 , 0xffffc000 , 0xffffc000 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x20811022 , 0x2200003 , 0x3000000 , 0x0 , /* AMD Vendor ID */
+ 0xfd000000 , 0xfe000000 , 0xfe004000 , 0xfe008000 , /* FB, GP, VG, DF */
+ 0xfe00c000 , 0x0 , 0x0 , 0x30100b , /* VIP */
+ 0x0 , 0x0 , 0x0 , 0x10e , /* INTA, IRQ14 for graphics accel */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x3d0 , 0x3c0 , 0xa0000 , 0x0 , /* VG IO, VG IO, EGA FB, MONO FB */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+static const ULONG gxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */
+ 0xff800008 , 0xffffc000 , 0xffffc000 , 0xffffc000 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x30100b , 0x2200003 , 0x3000000 , 0x0 , /* NSC Vendor ID */
+ 0xfd000000 , 0xfe000000 , 0xfe004000 , 0xfe008000 , /* FB, GP, VG, DF */
+ 0x0 , 0x0 , 0x0 , 0x30100b ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x3d0 , 0x3c0 , 0xa0000 , 0x0 , /* VG IO, VG IO, EGA FB, MONO FB */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+static const ULONG aes_hdr[] = { /* dev 1 function 2 - devfn = 0xa */
+ 0xffffc000 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x20821022 , 0x2a00006 , 0x10100000 , 0x8 , /* NSC Vendor ID */
+ 0xfe010000 , 0x0 , 0x0 , 0x0 , /* AES registers */
+ 0x0 , 0x0 , 0x0 , 0x20821022 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+
+static const ULONG isa_hdr[] = { /* dev f function 0 - devfn = 78 */
+ 0xfffffff9 , 0xffffff01 , 0xffffffc1 , 0xffffffe1 ,
+ 0xffffff81 , 0xffffffc1 , 0x0 , 0x0 ,
+
+ 0x20901022 , 0x2a00049 , 0x6010003 , 0x802000 ,
+ 0x18b1 , 0x1001 , 0x1801 , 0x1881 , /* SMB-8 GPIO-256 MFGPT-64 IRQ-32 */
+ 0x1401 , 0x1841 , 0x0 , 0x20901022 , /* PMS-128 ACPI-64 */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0xaa5b , /* interrupt steering */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+static const ULONG ac97_hdr[] = { /* dev f function 3 - devfn = 7b */
+ 0xffffff81 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x20931022 , 0x2a00041 , 0x4010001 , 0x0 ,
+ 0x1481 , 0x0 , 0x0 , 0x0 , /* I/O BAR-128 */
+ 0x0 , 0x0 , 0x0 , 0x20931022 ,
+ 0x0 , 0x0 , 0x0 , 0x205 , /* IntB , IRQ5 */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+static const ULONG ohci_hdr[] = { /* dev f function 4 - devfn = 7c */
+ 0xfffff000 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x20941022 , 0x2300006 , 0xc031002 , 0x0 ,
+ 0xfe01a000 , 0x0 , 0x0 , 0x0 , /* MEMBAR-1000 */
+ 0x0 , 0x0 , 0x0 , 0x20941022 ,
+ 0x0 , 0x40 , 0x0 , 0x40a , /* CapPtr INT-D, IRQ A */
+ 0xc8020001 , 0x0 , 0x0 , 0x0 , /* Capabilities - 40 is R/O, 44 is mask 8103 (power control) */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+static const ULONG ehci_hdr[] = { /* dev f function 5 - devfn = 7d */
+ 0xfffff000 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x20951022 , 0x2300006 , 0xc032002 , 0x0 ,
+ 0xfe01b000 , 0x0 , 0x0 , 0x0 , /* MEMBAR-1000 */
+ 0x0 , 0x0 , 0x0 , 0x20951022 ,
+ 0x0 , 0x40 , 0x0 , 0x40a , /* CapPtr INT-D, IRQ A */
+ 0xc8020001 , 0x0 , 0x0 , 0x0 , /* Capabilities - 40 is R/O, 44 is mask 8103 (power control) */
+#if 0
+ 0x1 , 0x40080000 , 0x0 , 0x0 , /* EECP - see section 2.1.7 of EHCI spec */
+#endif
+ 0x01000001 , 0x00000000 , 0x0 , 0x0 , /* EECP - see section 2.1.7 of EHCI spec */
+ 0x2020 , 0x0 , 0x0 , 0x0 , /* (EHCI page 8) 60 SBRN (R/O), 61 FLADJ (R/W), PORTWAKECAP */
+};
+
+static ULONG ff_loc = ~0;
+static ULONG zero_loc = 0;
+
+static int bar_probing = 0; /* Set after a write of ~0 to a BAR */
+
+static ULONG *hdr_addr(const ULONG *hdr, int reg)
+{
+ ULONG addr;
+
+ /*
+ * This is a little bit tricky. The header maps consist of
+ * 0x20 bytes of size masks, followed by 0x70 bytes of header data.
+ * In the normal case, when not probing a BAR's size, we want
+ * to access the header data, so we add 0x20 to the reg offset,
+ * thus skipping the size mask area.
+ * In the BAR probing case, we want to access the size mask for
+ * the BAR, so we subtract 0x10 (the config header offset for
+ * BAR0), and don't skip the size mask area.
+ */
+
+ addr = (ULONG)hdr + reg + (bar_probing ? -0x10 : 0x20);
+
+ if ( ((ULONG)addr - (ULONG)hdr) >= 0x90 )
+ {
+ DPRINT1("WARNING: out of bounds access: 0x%x, bar_probing %d, offset 0x%x\n",
+ (ULONG)addr - (ULONG)hdr, bar_probing, reg);
+ }
+
+ bar_probing = 0;
+ return (ULONG *)addr;
+}
+
+VOID NTAPI
+pci_olpc_read(ULONG bus, PCI_SLOT_NUMBER devfn, ULONG reg, ULONG len, PUCHAR value)
+{
+ ULONG *addr;
+
+ /*
+ * No device has config registers past 0x70, so we save table space
+ * by not storing entries for the nonexistent registers
+ */
+ if (reg >= 0x70)
+ {
+ addr = &zero_loc;
+ }
+ else
+ {
+ if (devfn.u.bits.DeviceNumber == 1)
+ {
+ switch (devfn.u.bits.FunctionNumber)
+ {
+ case 0 /* 0x8*/:
+ addr = hdr_addr(is_lx ? lxnb_hdr : gxnb_hdr, reg);
+ break;
+ case 1 /*0x9*/:
+ addr = hdr_addr(is_lx ? lxfb_hdr : gxfb_hdr, reg);
+ break;
+ case 2 /* 0xa*/:
+ addr = is_lx ? hdr_addr(aes_hdr, reg) : &ff_loc;
+ break;
+ default:
+ addr = &ff_loc;
+ break;
+ }
+ }
+ else
+ if (devfn.u.bits.DeviceNumber == 0xF)
+ {
+ switch (devfn.u.bits.FunctionNumber)
+ {
+ case 0 /*0x78*/:
+ addr = hdr_addr(isa_hdr, reg);
+ break;
+ case 3 /*0x7b*/:
+ addr = hdr_addr(ac97_hdr, reg);
+ break;
+ case 4 /*0x7c*/:
+ addr = hdr_addr(ohci_hdr, reg);
+ break;
+ case 5 /*0x7d*/:
+ addr = hdr_addr(ehci_hdr, reg);
+ break;
+ default:
+ addr = &zero_loc;
+ break;
+ }
+ }
+ else
+ {
+ addr = &ff_loc;
+ }
+ }
+
+ ASSERT(len == 1 || len == 2 || len == 4)
+ RtlCopyMemory(value, addr, len);
+}
+
+VOID NTAPI
+pci_olpc_write(ULONG bus, PCI_SLOT_NUMBER devfn, ULONG reg, ULONG len, PUCHAR value)
+{
+ /* XXX we may want to extend this to simulate EHCI power management */
+
+ /*
+ * Mostly we just discard writes, but if the write is a size probe
+ * (i.e. writing ~0 to a BAR), we remember it and arrange to return
+ * the appropriate size mask on the next read. This is cheating
+ * to some extent, because it depends on the fact that the next
+ * access after such a write will always be a read to the same BAR.
+ */
+
+ if ((reg >= 0x10) && (reg < 0x2c)) {
+ /* Write is to a BAR */
+ if (*(PULONG)value == ~0)
+ bar_probing = 1;
+ } else {
+ /*
+ * No warning on writes to ROM BAR, CMD, LATENCY_TIMER,
+ * CACHE_LINE_SIZE, or PM registers.
+ */
+ if ((reg != 0x30) && (reg != 0x04) && (reg != 0x0d) &&
+ (reg != 0x0c) && (reg != 0x44))
+ DbgPrint("OLPC PCI: Config write to devfn %x reg %x value %x\n", devfn, reg, *value);
+ }
+}
Propchange: branches/olpc/hal/halx86/generic/olpcpci.c
------------------------------------------------------------------------------
svn:eol-style = native
Modified: branches/olpc/hal/halx86/generic/pci.c
URL: http://svn.reactos.org/svn/reactos/branches/olpc/hal/halx86/generic/pci.c?rev=27787&r1=27786&r2=27787&view=diff
==============================================================================
--- branches/olpc/hal/halx86/generic/pci.c (original)
+++ branches/olpc/hal/halx86/generic/pci.c Mon Jul 23 17:43:57 2007
@@ -18,6 +18,10 @@
ULONG HalpMinPciBus, HalpMaxPciBus;
KSPIN_LOCK HalpPCIConfigLock;
PCI_CONFIG_HANDLER PCIConfigHandler;
+
+#define NB_SLOT 0x1 /* Northbridge - GX chip - Device 1 */
+#define SB_SLOT 0xf /* Southbridge - CS5536 chip - Device F */
+#define OLPC_SIMULATED(bus, devfn) ( ( (bus) == 0 ) && ( (devfn.u.bits.DeviceNumber == NB_SLOT) || (devfn.u.bits.DeviceNumber == SB_SLOT) ) )
/* PCI Operation Matrix */
UCHAR PCIDeref[4][4] =
@@ -107,6 +111,10 @@
NULL
};
+VOID NTAPI pci_olpc_read(ULONG bus, PCI_SLOT_NUMBER devfn, ULONG reg, ULONG len, PUCHAR value);
+VOID NTAPI pci_olpc_write(ULONG bus, PCI_SLOT_NUMBER devfn, ULONG reg, ULONG len, PUCHAR value);
+
+
/* TYPE 1 FUNCTIONS **********************************************************/
VOID
@@ -234,11 +242,26 @@
/* Find out the type of read/write we need to do */
i = PCIDeref[Offset % sizeof(ULONG)][Length % sizeof(ULONG)];
- /* Do the read/write and return the number of bytes */
- i = ConfigIO[i]((PPCIPBUSDATA)BusHandler->BusData,
- State,
- Buffer,
- Offset);
+ if (OLPC_SIMULATED(BusHandler->BusNumber, Slot))
+ {
+ /* Convert 0->ulong, 1->char, 2->short */
+ if (i == 0)
+ i = 4;
+
+ /* FIXME: Not really a good way to know if it's read or write... */
+ if (ConfigIO == PCIConfigHandler.ConfigRead)
+ pci_olpc_read(BusHandler->BusNumber, Slot, Offset, i, (PUCHAR)Buffer);
+ else
+ pci_olpc_write(BusHandler->BusNumber, Slot, Offset, i, (PUCHAR)Buffer);
+ }
+ else
+ {
+ /* Do the read/write and return the number of bytes */
+ i = ConfigIO[i]((PPCIPBUSDATA)BusHandler->BusData,
+ State,
+ Buffer,
+ Offset);
+ }
/* Increment the buffer position and offset, and decrease the length */
Offset += i;
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