[ros-diffs] [ros-arm-bringup] 41981: - Start re-defining the PTE and PDE structures for: - ARMv6 support. - Support of new ARM3 and overall portability. - Still have to find a better way to deal with the fact that PDE/PTE types are different on ARM. - Fix the current arm low-level mm implementation to use the new structures. - However parts of the code will now be totaly obsoleted by the new ARMv6 MMU support. - The ARM port now builds again.
ros-arm-bringup at svn.reactos.org
ros-arm-bringup at svn.reactos.org
Wed Jul 15 20:20:53 CEST 2009
Author: ros-arm-bringup
Date: Wed Jul 15 20:20:53 2009
New Revision: 41981
URL: http://svn.reactos.org/svn/reactos?rev=41981&view=rev
Log:
- Start re-defining the PTE and PDE structures for:
- ARMv6 support.
- Support of new ARM3 and overall portability.
- Still have to find a better way to deal with the fact that PDE/PTE types are different on ARM.
- Fix the current arm low-level mm implementation to use the new structures.
- However parts of the code will now be totaly obsoleted by the new ARMv6 MMU support.
- The ARM port now builds again.
Modified:
trunk/reactos/include/ndk/arm/mmtypes.h
trunk/reactos/ntoskrnl/include/internal/arm/mm.h
trunk/reactos/ntoskrnl/mm/arm/stubs.c
Modified: trunk/reactos/include/ndk/arm/mmtypes.h
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/ndk/arm/mmtypes.h?rev=41981&r1=41980&r2=41981&view=diff
==============================================================================
--- trunk/reactos/include/ndk/arm/mmtypes.h [iso-8859-1] (original)
+++ trunk/reactos/include/ndk/arm/mmtypes.h [iso-8859-1] Wed Jul 15 20:20:53 2009
@@ -185,7 +185,7 @@
ULONG filler1:1;
} MMPTE_LIST;
-typedef struct _MMPTE_HARDWARE
+typedef struct _MMPDE_HARDWARE // FIXFIX: Find a way to make this more portable
{
union
{
@@ -193,81 +193,50 @@
{
struct
{
- ULONG Type:2;
- ULONG Unused:30;
- } Fault;
- struct
- {
- ULONG Type:2;
- ULONG Ignored:2;
+ ULONG Valid:1;
+ ULONG Section:1;
+ ULONG Sbz:3;
+ ULONG Domain:4;
+ ULONG EccEnabled:1;
+ ULONG PageFrameNumber:22;
+ } Coarse;
+ struct
+ {
+ ULONG Coarse:1;
+ ULONG Valid:1;
+ ULONG Buffered:1;
+ ULONG Cached:1;
ULONG Reserved:1;
ULONG Domain:4;
- ULONG Ignored1:1;
- ULONG BaseAddress:22;
- } Coarse;
- struct
- {
- ULONG Type:2;
- ULONG Buffered:1;
- ULONG Cached:1;
- ULONG Reserved:1;
- ULONG Domain:4;
- ULONG Ignored:1;
+ ULONG EccEnabled:1;
ULONG Access:2;
- ULONG Ignored1:8;
- ULONG BaseAddress:12;
+ ULONG ExtendedAccess:3;
+ ULONG Sbz:3;
+ ULONG SuperSection:1;
+ ULONG Sbz1:1;
+ ULONG PageFrameNumber:12;
} Section;
- struct
- {
- ULONG Type:2;
- ULONG Reserved:3;
- ULONG Domain:4;
- ULONG Ignored:3;
- ULONG BaseAddress:20;
- } Fine;
- } L1;
- union
- {
- struct
- {
- ULONG Type:2;
- ULONG Unused:30;
- } Fault;
- struct
- {
- ULONG Type:2;
- ULONG Buffered:1;
- ULONG Cached:1;
- ULONG Access0:2;
- ULONG Access1:2;
- ULONG Access2:2;
- ULONG Access3:2;
- ULONG Ignored:4;
- ULONG BaseAddress:16;
- } Large;
- struct
- {
- ULONG Type:2;
- ULONG Buffered:1;
- ULONG Cached:1;
- ULONG Access0:2;
- ULONG Access1:2;
- ULONG Access2:2;
- ULONG Access3:2;
- ULONG BaseAddress:20;
- } Small;
- struct
- {
- ULONG Type:2;
- ULONG Buffered:1;
- ULONG Cached:1;
- ULONG Access0:2;
- ULONG Ignored:4;
- ULONG BaseAddress:22;
- } Tiny;
- } L2;
- ULONG AsUlong;
+ ULONG AsUlong;
+ } Hard;
+ } u;
+} MMPDE_HARDWARE, *PMMPDE_HARDWARE;
+
+typedef union _MMPTE_HARDWARE
+{
+ struct
+ {
+ ULONG ExecuteNever:1;
+ ULONG Valid:1;
+ ULONG Buffered:1;
+ ULONG Cached:1;
+ ULONG Access:2;
+ ULONG TypeExtension:3;
+ ULONG ExtendedAccess:1;
+ ULONG Shared:1;
+ ULONG NonGlobal:1;
+ ULONG PageFrameNumber:20;
};
+ ULONG AsUlong;
} MMPTE_HARDWARE, *PMMPTE_HARDWARE;
//
Modified: trunk/reactos/ntoskrnl/include/internal/arm/mm.h
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/include/internal/arm/mm.h?rev=41981&r1=41980&r2=41981&view=diff
==============================================================================
--- trunk/reactos/ntoskrnl/include/internal/arm/mm.h [iso-8859-1] (original)
+++ trunk/reactos/ntoskrnl/include/internal/arm/mm.h [iso-8859-1] Wed Jul 15 20:20:53 2009
@@ -7,6 +7,12 @@
#define PDE_SHIFT 20
#define PDE_SIZE (1 << PDE_SHIFT)
+
+//
+// FIXFIX: This is all wrong now!!!
+//
+
+
//
// Number of bits corresponding to the area that a coarse page table entry represents (4KB)
//
@@ -19,6 +25,11 @@
#define CPT_SHIFT 10
#define CPT_SIZE (1 << CPT_SHIFT)
+
+
+//
+// FIXFIX: This is all wrong now!!!
+//
typedef union _ARM_PTE
{
union
@@ -143,6 +154,11 @@
ManagerDomain
} ARM_DOMAIN;
+
+//
+// FIXFIX: This is all wrong now!!!
+//
+
//
// Take 0x80812345 and extract:
// PTE_BASE[0x808][0x12]
@@ -153,7 +169,7 @@
((((ULONG)(x) >> 12) & 0xFF) << 2))
#define MiGetPdeAddress(x) \
- (PMMPTE)(PDE_BASE + \
+ (PMMPDE_HARDWARE)(PDE_BASE + \
(((ULONG)(x) >> 20) << 2))
#define MiGetPdeOffset(x) (((ULONG)(x)) >> 22)
@@ -165,4 +181,36 @@
struct _EPROCESS;
PULONG MmGetPageDirectory(VOID);
+
+//
+// FIXME: THESE ARE WRONG ATM.
+//
+#define MiAddressToPde(x) \
+((PMMPTE)(((((ULONG)(x)) >> 22) << 2) + PDE_BASE))
+#define MiAddressToPte(x) \
+((PMMPTE)(((((ULONG)(x)) >> 12) << 2) + PTE_BASE))
+#define MiAddressToPteOffset(x) \
+((((ULONG)(x)) << 10) >> 22)
+
+//
+// Convert a PTE into a corresponding address
+//
+#define MiPteToAddress(PTE) ((PVOID)((ULONG)(PTE) << 10))
+
+#define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
+#define ADDR_TO_PDE_OFFSET(v) ((((ULONG)(v)) / (1024 * PAGE_SIZE)))
+#define ADDR_TO_PTE_OFFSET(v) ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE)
+
+#define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.NonGlobal = 1)
+#define MI_MAKE_DIRTY_PAGE(x)
+#define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.Cached = 0)
+#define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.Buffered = 0)
+#define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.Buffered = 1)
+#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.ExtendedAccess == 0)
+#define MI_IS_PAGE_COPY_ON_WRITE(x)FALSE
+#define MI_IS_PAGE_DIRTY(x) TRUE
+
+/* Easy accessing PFN in PTE */
+#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
+
#endif
Modified: trunk/reactos/ntoskrnl/mm/arm/stubs.c
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/mm/arm/stubs.c?rev=41981&r1=41980&r2=41981&view=diff
==============================================================================
--- trunk/reactos/ntoskrnl/mm/arm/stubs.c [iso-8859-1] (original)
+++ trunk/reactos/ntoskrnl/mm/arm/stubs.c [iso-8859-1] Wed Jul 15 20:20:53 2009
@@ -15,7 +15,8 @@
/* GLOBALS ********************************************************************/
ULONG MmGlobalKernelPageDirectory[1024];
-MMPTE MiArmTemplatePte, MiArmTemplatePde;
+MMPTE MiArmTemplatePte;
+MMPDE_HARDWARE MiArmTemplatePde;
/* PRIVATE FUNCTIONS **********************************************************/
@@ -67,8 +68,10 @@
IN BOOLEAN Create)
{
//ULONG PdeOffset;
- PMMPTE PointerPde, PointerPte;
- MMPTE TempPde, TempPte;
+ PMMPTE PointerPte;
+ PMMPDE_HARDWARE PointerPde;
+ MMPDE_HARDWARE TempPde;
+ MMPTE TempPte;
NTSTATUS Status;
PFN_NUMBER Pfn;
@@ -95,7 +98,7 @@
// Get the PDE
//
PointerPde = MiGetPdeAddress(Address);
- if (PointerPde->u.Hard.L1.Fault.Type == FaultPte)
+ if (PointerPde->u.Hard.Coarse.Valid)
{
//
// Invalid PDE, is this a kernel address?
@@ -125,13 +128,13 @@
//
// Setup the PFN
//
- TempPde.u.Hard.L1.Coarse.BaseAddress = (Pfn << PAGE_SHIFT) >> CPT_SHIFT;
+ TempPde.u.Hard.Coarse.PageFrameNumber = (Pfn << PAGE_SHIFT) >> CPT_SHIFT;
//
// Write the PDE
//
- ASSERT(PointerPde->u.Hard.L1.Fault.Type == FaultPte);
- ASSERT(TempPde.u.Hard.L1.Coarse.Type == CoarsePte);
+ ASSERT(PointerPde->u.Hard.Coarse.Valid == 0);
+ ASSERT(TempPde.u.Hard.Coarse.Valid == 1);
*PointerPde = TempPde;
//
@@ -153,13 +156,13 @@
//
// Write the PFN of the PDE
//
- TempPte.u.Hard.L2.Small.BaseAddress = Pfn;
+ TempPte.u.Hard.PageFrameNumber = Pfn;
//
// Write the PTE
//
- ASSERT(PointerPte->u.Hard.L2.Fault.Type == FaultPte);
- ASSERT(TempPte.u.Hard.L2.Small.Type == SmallPte);
+ ASSERT(PointerPte->u.Hard.Valid == 0);
+ ASSERT(TempPte.u.Hard.Valid == 1);
*PointerPte = TempPte;
/////
}
@@ -191,12 +194,12 @@
//
// Make the entry valid
//
- TempPte.u.Hard.AsUlong = 0xDEADBEEF;
+ TempPde.u.Hard.AsUlong = 0xDEADBEEF;
//
// Set it
//
- *PointerPde = TempPte;
+ *PointerPde = TempPde;
}
}
@@ -239,7 +242,7 @@
MmDeletePageTable(IN PEPROCESS Process,
IN PVOID Address)
{
- PMMPTE PointerPde;
+ PMMPDE_HARDWARE PointerPde;
//
// Not valid for kernel addresses
@@ -266,24 +269,24 @@
//
// On ARM, we use a section mapping for the original low-memory mapping
//
- if ((Address) || (PointerPde->u.Hard.L1.Section.Type != SectionPte))
+ if ((Address) || (PointerPde->u.Hard.Section.Valid == 0))
{
//
// Make sure it's valid
//
- ASSERT(PointerPde->u.Hard.L1.Coarse.Type == CoarsePte);
+ ASSERT(PointerPde->u.Hard.Coarse.Valid == 1);
}
//
// Clear the PDE
//
PointerPde->u.Hard.AsUlong = 0;
- ASSERT(PointerPde->u.Hard.L1.Fault.Type == FaultPte);
+ ASSERT(PointerPde->u.Hard.Coarse.Valid == 0);
//
// Invalidate the TLB entry
//
- MiFlushTlb(PointerPde, MiGetPteAddress(Address));
+ MiFlushTlb((PMMPTE)PointerPde, MiGetPteAddress(Address));
}
BOOLEAN
@@ -295,8 +298,8 @@
NTSTATUS Status;
ULONG i;
PFN_NUMBER Pfn[2];
- PMMPTE PageDirectory, PointerPde;
- MMPTE TempPde;
+ PMMPDE_HARDWARE PageDirectory, PointerPde;
+ MMPDE_HARDWARE TempPde;
ASSERT(FALSE);
//
@@ -329,27 +332,27 @@
// Setup the PDE for the table base
//
TempPde = MiArmTemplatePde;
- TempPde.u.Hard.L1.Coarse.BaseAddress = (Pfn[0] << PAGE_SHIFT) >> CPT_SHIFT;
+ TempPde.u.Hard.Coarse.PageFrameNumber = (Pfn[0] << PAGE_SHIFT) >> CPT_SHIFT;
PointerPde = &PageDirectory[MiGetPdeOffset(PTE_BASE)];
//
// Write the PDE
//
- ASSERT(PointerPde->u.Hard.L1.Fault.Type == FaultPte);
- ASSERT(TempPde.u.Hard.L1.Coarse.Type == CoarsePte);
+ ASSERT(PointerPde->u.Hard.Coarse.Valid == 0);
+ ASSERT(TempPde.u.Hard.Coarse.Valid == 1);
*PointerPde = TempPde;
//
// Setup the PDE for the hyperspace
//
- TempPde.u.Hard.L1.Coarse.BaseAddress = (Pfn[1] << PAGE_SHIFT) >> CPT_SHIFT;
+ TempPde.u.Hard.Coarse.PageFrameNumber = (Pfn[1] << PAGE_SHIFT) >> CPT_SHIFT;
PointerPde = &PageDirectory[MiGetPdeOffset(HYPER_SPACE)];
//
// Write the PDE
//
- ASSERT(PointerPde->u.Hard.L1.Fault.Type == FaultPte);
- ASSERT(TempPde.u.Hard.L1.Coarse.Type == CoarsePte);
+ ASSERT(PointerPde->u.Hard.Coarse.Valid == 0);
+ ASSERT(TempPde.u.Hard.Coarse.Valid == 1);
*PointerPde = TempPde;
//
@@ -515,13 +518,13 @@
//
// Set the PFN
//
- TempPte.u.Hard.L2.Small.BaseAddress = *Pages++;
+ TempPte.u.Hard.PageFrameNumber = *Pages++;
//
// Write the PTE
//
- ASSERT(PointerPte->u.Hard.L2.Fault.Type == FaultPte);
- ASSERT(TempPte.u.Hard.L2.Small.Type == SmallPte);
+ ASSERT(PointerPte->u.Hard.Valid == 0);
+ ASSERT(TempPte.u.Hard.Valid == 1);
*PointerPte = TempPte;
//
@@ -626,7 +629,7 @@
// Get the PTE
//
PointerPte = MiGetPageTableForProcess(NULL, Address, FALSE);
- if ((PointerPte) && (PointerPte->u.Hard.L2.Fault.Type != FaultPte))
+ if ((PointerPte) && (PointerPte->u.Hard.Valid))
{
//
// Destroy it
@@ -672,7 +675,7 @@
//
// Unmap the PFN
//
- Pfn = Pte.u.Hard.L2.Small.BaseAddress;
+ Pfn = Pte.u.Hard.PageFrameNumber;
if (Pfn) MmMarkPageUnmapped(Pfn);
//
@@ -726,12 +729,12 @@
// Get the PTE
//
Pte = MiGetPageEntryForProcess(Process, Address);
- if (Pte.u.Hard.L2.Fault.Type == FaultPte) return 0;
+ if (Pte.u.Hard.Valid == 0) return 0;
//
// Return PFN
//
- return Pte.u.Hard.L2.Small.BaseAddress;
+ return Pte.u.Hard.PageFrameNumber;
}
BOOLEAN
@@ -779,7 +782,7 @@
//
// Fault PTEs are 0, which is FALSE (non-present)
//
- return MiGetPageEntryForProcess(Process, Address).u.Hard.L2.Fault.Type;
+ return MiGetPageEntryForProcess(Process, Address).u.Hard.Valid;
}
BOOLEAN
@@ -795,9 +798,9 @@
Pte = MiGetPageEntryForProcess(Process, Address);
//
- // Make sure it's valid, but faulting
- //
- return (Pte.u.Hard.L2.Fault.Type == FaultPte) && (Pte.u.Hard.AsUlong);
+ // Make sure it exists, but is faulting
+ //
+ return (Pte.u.Hard.Valid == 0) && (Pte.u.Hard.AsUlong);
}
ULONG
@@ -934,10 +937,10 @@
//
// ARM Hack while we still use a section PTE
//
- PMMPTE PointerPte;
- PointerPte = MiGetPdeAddress(PCR);
- ASSERT(PointerPte->u.Hard.L1.Section.Type == SectionPte);
- PhysicalAddress.QuadPart = PointerPte->u.Hard.L1.Section.BaseAddress;
+ PMMPDE_HARDWARE PointerPde;
+ PointerPde = MiGetPdeAddress(PCR);
+ ASSERT(PointerPde->u.Hard.Section.Valid == 1);
+ PhysicalAddress.QuadPart = PointerPde->u.Hard.Section.PageFrameNumber;
PhysicalAddress.QuadPart <<= CPT_SHIFT;
PhysicalAddress.LowPart += BYTE_OFFSET(Address);
return PhysicalAddress;
@@ -947,13 +950,12 @@
// Get the PTE
//
Pte = MiGetPageEntryForProcess(NULL, Address);
- if ((Pte.u.Hard.AsUlong) && (Pte.u.Hard.L2.Fault.Type != FaultPte))
+ if (Pte.u.Hard.Valid)
{
//
// Return the information
//
- ASSERT(Pte.u.Hard.L2.Small.Type == SmallPte);
- PhysicalAddress.QuadPart = Pte.u.Hard.L2.Small.BaseAddress;
+ PhysicalAddress.QuadPart = Pte.u.Hard.PageFrameNumber;
PhysicalAddress.QuadPart <<= PAGE_SHIFT;
PhysicalAddress.LowPart += BYTE_OFFSET(Address);
}
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