[ros-diffs] [tkreuzer] 46447: [HAL] - Move architecture specific files into appropriate folders - Move UP specific files into up folder
tkreuzer at svn.reactos.org
tkreuzer at svn.reactos.org
Thu Mar 25 20:23:09 CET 2010
Author: tkreuzer
Date: Thu Mar 25 20:23:09 2010
New Revision: 46447
URL: http://svn.reactos.org/svn/reactos?rev=46447&view=rev
Log:
[HAL]
- Move architecture specific files into appropriate folders
- Move UP specific files into up folder
Added:
trunk/reactos/hal/halx86/generic/amd64/ (with props)
trunk/reactos/hal/halx86/generic/i386/ (with props)
trunk/reactos/hal/halx86/generic/i386/portio.c
- copied unchanged from r46439, trunk/reactos/hal/halx86/generic/portio.c
trunk/reactos/hal/halx86/generic/i386/systimer.S
- copied unchanged from r46439, trunk/reactos/hal/halx86/generic/systimer.S
trunk/reactos/hal/halx86/generic/i386/trap.S
- copied unchanged from r46439, trunk/reactos/hal/halx86/generic/trap.S
trunk/reactos/hal/halx86/mp/amd64/ (with props)
trunk/reactos/hal/halx86/mp/i386/ (with props)
trunk/reactos/hal/halx86/mp/i386/mps.S
- copied unchanged from r46439, trunk/reactos/hal/halx86/mp/mps.S
trunk/reactos/hal/halx86/mp/i386/mpsboot.asm
- copied unchanged from r46439, trunk/reactos/hal/halx86/mp/mpsboot.asm
trunk/reactos/hal/halx86/mp/i386/mpsirql.c
- copied unchanged from r46446, trunk/reactos/hal/halx86/mp/mpsirql.c
trunk/reactos/hal/halx86/up/pic.c
- copied unchanged from r46439, trunk/reactos/hal/halx86/generic/pic.c
trunk/reactos/hal/halx86/up/processor.c
- copied unchanged from r46439, trunk/reactos/hal/halx86/generic/processor.c
Removed:
trunk/reactos/hal/halx86/generic/pic.c
trunk/reactos/hal/halx86/generic/portio.c
trunk/reactos/hal/halx86/generic/processor.c
trunk/reactos/hal/halx86/generic/systimer.S
trunk/reactos/hal/halx86/generic/trap.S
trunk/reactos/hal/halx86/mp/mps.S
trunk/reactos/hal/halx86/mp/mpsboot.asm
trunk/reactos/hal/halx86/mp/mpsirql.c
Modified:
trunk/reactos/hal/hal.rbuild
trunk/reactos/hal/halx86/hal_generic.rbuild
trunk/reactos/hal/halx86/hal_generic_up.rbuild
trunk/reactos/hal/halx86/halmps.rbuild
Modified: trunk/reactos/hal/hal.rbuild
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/hal.rbuild?rev=46447&r1=46446&r2=46447&view=diff
==============================================================================
--- trunk/reactos/hal/hal.rbuild [iso-8859-1] (original)
+++ trunk/reactos/hal/hal.rbuild [iso-8859-1] Thu Mar 25 20:23:09 2010
@@ -2,10 +2,16 @@
<!DOCTYPE group SYSTEM "../tools/rbuild/project.dtd">
<group xmlns:xi="http://www.w3.org/2001/XInclude">
- <if property="ARCH" value="i386">
- <directory name="halx86">
- <xi:include href="halx86/directory.rbuild" />
- </directory>
+ <if property="ARCH" value="i386">
+ <directory name="halx86">
+ <xi:include href="halx86/directory.rbuild" />
+ </directory>
+ </if>
+
+ <if property="ARCH" value="amd64">
+ <directory name="halx86">
+ <xi:include href="halx86/directory.rbuild" />
+ </directory>
</if>
<if property="ARCH" value="powerpc">
Propchange: trunk/reactos/hal/halx86/generic/amd64/
------------------------------------------------------------------------------
--- bugtraq:logregex (added)
+++ bugtraq:logregex Thu Mar 25 20:23:09 2010
@@ -1,0 +1,2 @@
+([Ii]ssue|[Bb]ug)s? #?(\d+)(,? ?#?(\d+))*(,? ?(and |or )?#?(\d+))?
+(\d+)
Propchange: trunk/reactos/hal/halx86/generic/amd64/
------------------------------------------------------------------------------
bugtraq:message = See issue #%BUGID% for more details.
Propchange: trunk/reactos/hal/halx86/generic/amd64/
------------------------------------------------------------------------------
bugtraq:url = http://www.reactos.org/bugzilla/show_bug.cgi?id=%BUGID%
Propchange: trunk/reactos/hal/halx86/generic/amd64/
------------------------------------------------------------------------------
tsvn:logminsize = 10
Propchange: trunk/reactos/hal/halx86/generic/i386/
------------------------------------------------------------------------------
--- bugtraq:logregex (added)
+++ bugtraq:logregex Thu Mar 25 20:23:09 2010
@@ -1,0 +1,2 @@
+([Ii]ssue|[Bb]ug)s? #?(\d+)(,? ?#?(\d+))*(,? ?(and |or )?#?(\d+))?
+(\d+)
Propchange: trunk/reactos/hal/halx86/generic/i386/
------------------------------------------------------------------------------
bugtraq:message = See issue #%BUGID% for more details.
Propchange: trunk/reactos/hal/halx86/generic/i386/
------------------------------------------------------------------------------
bugtraq:url = http://www.reactos.org/bugzilla/show_bug.cgi?id=%BUGID%
Propchange: trunk/reactos/hal/halx86/generic/i386/
------------------------------------------------------------------------------
tsvn:logminsize = 10
Removed: trunk/reactos/hal/halx86/generic/pic.c
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/generic/pic.c?rev=46446&view=auto
==============================================================================
--- trunk/reactos/hal/halx86/generic/pic.c [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/generic/pic.c (removed)
@@ -1,1363 +1,0 @@
-/*
- * PROJECT: ReactOS HAL
- * LICENSE: BSD - See COPYING.ARM in the top level directory
- * FILE: hal/halx86/generic/pic.c
- * PURPOSE: HAL PIC Management and Control Code
- * PROGRAMMERS: ReactOS Portable Systems Group
- */
-
-/* INCLUDES *******************************************************************/
-
-#include <hal.h>
-#define NDEBUG
-#include <debug.h>
-
-/* GLOBALS ********************************************************************/
-
-#ifndef _MINIHAL_
-/*
- * This table basically keeps track of level vs edge triggered interrupts.
- * Windows has 250+ entries, but it seems stupid to replicate that since the PIC
- * can't actually have that many.
- *
- * When a level interrupt is registered, the respective pointer in this table is
- * modified to point to a dimiss routine for level interrupts instead.
- *
- * The other thing this table does is special case IRQ7, IRQ13 and IRQ15:
- *
- * - If an IRQ line is deasserted before it is acknowledged due to a noise spike
- * generated by an expansion device (since the IRQ line is low during the 1st
- * acknowledge bus cycle), the i8259 will keep the line low for at least 100ns
- * When the spike passes, a pull-up resistor will return the IRQ line to high.
- * Since the PIC requires the input be high until the first acknowledge, the
- * i8259 knows that this was a spurious interrupt, and on the second interrupt
- * acknowledge cycle, it reports this to the CPU. Since no valid interrupt has
- * actually happened Intel hardcoded the chip to report IRQ7 on the master PIC
- * and IRQ15 on the slave PIC (IR7 either way).
- *
- * "ISA System Architecture", 3rd Edition, states that these cases should be
- * handled by reading the respective Interrupt Service Request (ISR) bits from
- * the affected PIC, and validate whether or not IR7 is set. If it isn't, then
- * the interrupt is spurious and should be ignored.
- *
- * Note that for a spurious IRQ15, we DO have to send an EOI to the master for
- * IRQ2 since the line was asserted by the slave when it received the spurious
- * IRQ15!
- *
- * - When the 80287/80387 math co-processor generates an FPU/NPX trap, this is
- * connected to IRQ13, so we have to clear the busy latch on the NPX port.
- */
-PHAL_DISMISS_INTERRUPT HalpSpecialDismissTable[16] =
-{
- HalpDismissIrqGeneric,
- HalpDismissIrqGeneric,
- HalpDismissIrqGeneric,
- HalpDismissIrqGeneric,
- HalpDismissIrqGeneric,
- HalpDismissIrqGeneric,
- HalpDismissIrqGeneric,
- HalpDismissIrq07,
- HalpDismissIrqGeneric,
- HalpDismissIrqGeneric,
- HalpDismissIrqGeneric,
- HalpDismissIrqGeneric,
- HalpDismissIrqGeneric,
- HalpDismissIrq13,
- HalpDismissIrqGeneric,
- HalpDismissIrq15
-};
-
-/*
- * These are the level IRQ dismissal functions that get copied in the table
- * above if the given IRQ is actually level triggered.
- */
-PHAL_DISMISS_INTERRUPT HalpSpecialDismissLevelTable[16] =
-{
- HalpDismissIrqLevel,
- HalpDismissIrqLevel,
- HalpDismissIrqLevel,
- HalpDismissIrqLevel,
- HalpDismissIrqLevel,
- HalpDismissIrqLevel,
- HalpDismissIrqLevel,
- HalpDismissIrq07Level,
- HalpDismissIrqLevel,
- HalpDismissIrqLevel,
- HalpDismissIrqLevel,
- HalpDismissIrqLevel,
- HalpDismissIrqLevel,
- HalpDismissIrq13Level,
- HalpDismissIrqLevel,
- HalpDismissIrq15Level
-};
-
-/* This table contains the static x86 PIC mapping between IRQLs and IRQs */
-ULONG KiI8259MaskTable[32] =
-{
-#ifdef __GNUC__
-#if __GNUC__ * 100 + __GNUC_MINOR__ >= 404
- /*
- * It Device IRQLs only start at 4 or higher, so these are just software
- * IRQLs that don't really change anything on the hardware
- */
- 0b00000000000000000000000000000000, /* IRQL 0 */
- 0b00000000000000000000000000000000, /* IRQL 1 */
- 0b00000000000000000000000000000000, /* IRQL 2 */
- 0b00000000000000000000000000000000, /* IRQL 3 */
-
- /*
- * These next IRQLs are actually useless from the PIC perspective, because
- * with only 2 PICs, the mask you can send them is only 8 bits each, for 16
- * bits total, so these IRQLs are masking off a phantom PIC.
- */
- 0b11111111100000000000000000000000, /* IRQL 4 */
- 0b11111111110000000000000000000000, /* IRQL 5 */
- 0b11111111111000000000000000000000, /* IRQL 6 */
- 0b11111111111100000000000000000000, /* IRQL 7 */
- 0b11111111111110000000000000000000, /* IRQL 8 */
- 0b11111111111111000000000000000000, /* IRQL 9 */
- 0b11111111111111100000000000000000, /* IRQL 10 */
- 0b11111111111111110000000000000000, /* IRQL 11 */
-
- /*
- * Okay, now we're finally starting to mask off IRQs on the slave PIC, from
- * IRQ15 to IRQ8. This means the higher-level IRQs get less priority in the
- * IRQL sense.
- */
- 0b11111111111111111000000000000000, /* IRQL 12 */
- 0b11111111111111111100000000000000, /* IRQL 13 */
- 0b11111111111111111110000000000000, /* IRQL 14 */
- 0b11111111111111111111000000000000, /* IRQL 15 */
- 0b11111111111111111111100000000000, /* IRQL 16 */
- 0b11111111111111111111110000000000, /* IRQL 17 */
- 0b11111111111111111111111000000000, /* IRQL 18 */
- 0b11111111111111111111111000000000, /* IRQL 19 */
-
- /*
- * Now we mask off the IRQs on the master. Notice the 0 "droplet"? You might
- * have also seen that IRQL 18 and 19 are essentially equal as far as the
- * PIC is concerned. That bit is actually IRQ8, which happens to be the RTC.
- * The RTC will keep firing as long as we don't reach PROFILE_LEVEL which
- * actually kills it. The RTC clock (unlike the system clock) is used by the
- * profiling APIs in the HAL, so that explains the logic.
- */
- 0b11111111111111111111111010000000, /* IRQL 20 */
- 0b11111111111111111111111011000000, /* IRQL 21 */
- 0b11111111111111111111111011100000, /* IRQL 22 */
- 0b11111111111111111111111011110000, /* IRQL 23 */
- 0b11111111111111111111111011111000, /* IRQL 24 */
- 0b11111111111111111111111011111000, /* IRQL 25 */
- 0b11111111111111111111111011111010, /* IRQL 26 */
- 0b11111111111111111111111111111010, /* IRQL 27 */
-
- /*
- * IRQL 24 and 25 are actually identical, so IRQL 28 is actually the last
- * IRQL to modify a bit on the master PIC. It happens to modify the very
- * last of the IRQs, IRQ0, which corresponds to the system clock interval
- * timer that keeps track of time (the Windows heartbeat). We only want to
- * turn this off at a high-enough IRQL, which is why IRQLs 24 and 25 are the
- * same to give this guy a chance to come up higher. Note that IRQL 28 is
- * called CLOCK2_LEVEL, which explains the usage we just explained.
- */
- 0b11111111111111111111111111111011, /* IRQL 28 */
-
- /*
- * We have finished off with the PIC so there's nothing left to mask at the
- * level of these IRQLs, making them only logical IRQLs on x86 machines.
- * Note that we have another 0 "droplet" you might've caught since IRQL 26.
- * In this case, it's the 2nd bit that never gets turned off, which is IRQ2,
- * the cascade IRQ that we use to bridge the slave PIC with the master PIC.
- * We never want to turn it off, so no matter the IRQL, it will be set to 0.
- */
- 0b11111111111111111111111111111011, /* IRQL 29 */
- 0b11111111111111111111111111111011, /* IRQL 30 */
- 0b11111111111111111111111111111011 /* IRQL 31 */
-#else
- 0, /* IRQL 0 */
- 0, /* IRQL 1 */
- 0, /* IRQL 2 */
- 0, /* IRQL 3 */
- 0xFF800000, /* IRQL 4 */
- 0xFFC00000, /* IRQL 5 */
- 0xFFE00000, /* IRQL 6 */
- 0xFFF00000, /* IRQL 7 */
- 0xFFF80000, /* IRQL 8 */
- 0xFFFC0000, /* IRQL 9 */
- 0xFFFE0000, /* IRQL 10 */
- 0xFFFF0000, /* IRQL 11 */
- 0xFFFF8000, /* IRQL 12 */
- 0xFFFFC000, /* IRQL 13 */
- 0xFFFFE000, /* IRQL 14 */
- 0xFFFFF000, /* IRQL 15 */
- 0xFFFFF800, /* IRQL 16 */
- 0xFFFFFC00, /* IRQL 17 */
- 0xFFFFFE00, /* IRQL 18 */
- 0xFFFFFE00, /* IRQL 19 */
- 0xFFFFFE80, /* IRQL 20 */
- 0xFFFFFEC0, /* IRQL 21 */
- 0xFFFFFEE0, /* IRQL 22 */
- 0xFFFFFEF0, /* IRQL 23 */
- 0xFFFFFEF8, /* IRQL 24 */
- 0xFFFFFEF8, /* IRQL 25 */
- 0xFFFFFEFA, /* IRQL 26 */
- 0xFFFFFFFA, /* IRQL 27 */
- 0xFFFFFFFB, /* IRQL 28 */
- 0xFFFFFFFB, /* IRQL 29 */
- 0xFFFFFFFB, /* IRQL 30 */
- 0xFFFFFFFB /* IRQL 31 */
-#endif
-#endif
-};
-
-/* This table indicates which IRQs, if pending, can preempt a given IRQL level */
-ULONG FindHigherIrqlMask[32] =
-{
-#ifdef __GNUC__
-#if __GNUC__ * 100 + __GNUC_MINOR__ >= 404
- /*
- * Software IRQLs, at these levels all hardware interrupts can preempt.
- * Each higher IRQL simply enables which software IRQL can preempt the
- * current level.
- */
- 0b11111111111111111111111111111110, /* IRQL 0 */
- 0b11111111111111111111111111111100, /* IRQL 1 */
- 0b11111111111111111111111111111000, /* IRQL 2 */
-
- /*
- * IRQL3 means only hardware IRQLs can now preempt. These last 4 zeros will
- * then continue throughout the rest of the list, trickling down.
- */
- 0b11111111111111111111111111110000, /* IRQL 3 */
-
- /*
- * Just like in the previous list, these masks don't really mean anything
- * since we've only got two PICs with 16 possible IRQs total
- */
- 0b00000111111111111111111111110000, /* IRQL 4 */
- 0b00000011111111111111111111110000, /* IRQL 5 */
- 0b00000001111111111111111111110000, /* IRQL 6 */
- 0b00000000111111111111111111110000, /* IRQL 7 */
- 0b00000000011111111111111111110000, /* IRQL 8 */
- 0b00000000001111111111111111110000, /* IRQL 9 */
- 0b00000000000111111111111111110000, /* IRQL 10 */
-
- /*
- * Now we start progressivly limiting which slave PIC interrupts have the
- * right to preempt us at each level.
- */
- 0b00000000000011111111111111110000, /* IRQL 11 */
- 0b00000000000001111111111111110000, /* IRQL 12 */
- 0b00000000000000111111111111110000, /* IRQL 13 */
- 0b00000000000000011111111111110000, /* IRQL 14 */
- 0b00000000000000001111111111110000, /* IRQL 15 */
- 0b00000000000000000111111111110000, /* IRQL 16 */
- 0b00000000000000000011111111110000, /* IRQL 17 */
- 0b00000000000000000001111111110000, /* IRQL 18 */
- 0b00000000000000000001111111110000, /* IRQL 19 */
-
- /*
- * Also recall from the earlier table that IRQL 18/19 are treated the same
- * in order to spread the masks better thoughout the 32 IRQLs and to reflect
- * the fact that some bits will always stay on until much higher IRQLs since
- * they are system-critical. One such example is the 1 bit that you start to
- * see trickling down here. This is IRQ8, the RTC timer used for profiling,
- * so it will always preempt until we reach PROFILE_LEVEL.
- */
- 0b00000000000000000001011111110000, /* IRQL 20 */
- 0b00000000000000000001001111110000, /* IRQL 20 */
- 0b00000000000000000001000111110000, /* IRQL 22 */
- 0b00000000000000000001000011110000, /* IRQL 23 */
- 0b00000000000000000001000001110000, /* IRQL 24 */
- 0b00000000000000000001000000110000, /* IRQL 25 */
- 0b00000000000000000001000000010000, /* IRQL 26 */
-
- /* At this point, only the clock (IRQ0) can still preempt... */
- 0b00000000000000000000000000010000, /* IRQL 27 */
-
- /* And any higher than that there's no relation with hardware PICs anymore */
- 0b00000000000000000000000000000000, /* IRQL 28 */
- 0b00000000000000000000000000000000, /* IRQL 29 */
- 0b00000000000000000000000000000000, /* IRQL 30 */
- 0b00000000000000000000000000000000, /* IRQL 31 */
-#else
- 0xFFFFFFFE, /* IRQL 0 */
- 0xFFFFFFFC, /* IRQL 1 */
- 0xFFFFFFF8, /* IRQL 2 */
- 0xFFFFFFF0, /* IRQL 3 */
- 0x7FFFFF0, /* IRQL 4 */
- 0x3FFFFF0, /* IRQL 5 */
- 0x1FFFFF0, /* IRQL 6 */
- 0x0FFFFF0, /* IRQL 7 */
- 0x7FFFF0, /* IRQL 8 */
- 0x3FFFF0, /* IRQL 9 */
- 0x1FFFF0, /* IRQL 10 */
- 0x0FFFF0, /* IRQL 11 */
- 0x7FFF0, /* IRQL 12 */
- 0x3FFF0, /* IRQL 13 */
- 0x1FFF0, /* IRQL 14 */
- 0x0FFF0, /* IRQL 15 */
- 0x7FF0, /* IRQL 16 */
- 0x3FF0, /* IRQL 17 */
- 0x1FF0, /* IRQL 18 */
- 0x1FF0, /* IRQL 19 */
- 0x17F0, /* IRQL 20 */
- 0x13F0, /* IRQL 21 */
- 0x11F0, /* IRQL 22 */
- 0x10F0, /* IRQL 23 */
- 0x1070, /* IRQL 24 */
- 0x1030, /* IRQL 25 */
- 0x1010, /* IRQL 26 */
- 0x10, /* IRQL 27 */
- 0, /* IRQL 28 */
- 0, /* IRQL 29 */
- 0, /* IRQL 30 */
- 0 /* IRQL 31 */
-#endif
-#endif
-};
-
-/* Denotes minimum required IRQL before we can process pending SW interrupts */
-KIRQL SWInterruptLookUpTable[8] =
-{
- PASSIVE_LEVEL, /* IRR 0 */
- PASSIVE_LEVEL, /* IRR 1 */
- APC_LEVEL, /* IRR 2 */
- APC_LEVEL, /* IRR 3 */
- DISPATCH_LEVEL, /* IRR 4 */
- DISPATCH_LEVEL, /* IRR 5 */
- DISPATCH_LEVEL, /* IRR 6 */
- DISPATCH_LEVEL /* IRR 7 */
-};
-
-#define HalpDelayedHardwareInterrupt(x) \
- VOID HalpHardwareInterrupt##x(VOID); \
- VOID \
- HalpHardwareInterrupt##x(VOID) \
- { \
- asm volatile ("int $%c0\n"::"i"(PRIMARY_VECTOR_BASE + x)); \
- }
-
-/* Pending/delayed hardware interrupt handlers */
-HalpDelayedHardwareInterrupt(0);
-HalpDelayedHardwareInterrupt(1);
-HalpDelayedHardwareInterrupt(2);
-HalpDelayedHardwareInterrupt(3);
-HalpDelayedHardwareInterrupt(4);
-HalpDelayedHardwareInterrupt(5);
-HalpDelayedHardwareInterrupt(6);
-HalpDelayedHardwareInterrupt(7);
-HalpDelayedHardwareInterrupt(8);
-HalpDelayedHardwareInterrupt(9);
-HalpDelayedHardwareInterrupt(10);
-HalpDelayedHardwareInterrupt(11);
-HalpDelayedHardwareInterrupt(12);
-HalpDelayedHardwareInterrupt(13);
-HalpDelayedHardwareInterrupt(14);
-HalpDelayedHardwareInterrupt(15);
-
-/* Handlers for pending interrupts */
-PHAL_SW_INTERRUPT_HANDLER SWInterruptHandlerTable[20] =
-{
- KiUnexpectedInterrupt,
- HalpApcInterrupt,
- HalpDispatchInterrupt2,
- KiUnexpectedInterrupt,
- HalpHardwareInterrupt0,
- HalpHardwareInterrupt1,
- HalpHardwareInterrupt2,
- HalpHardwareInterrupt3,
- HalpHardwareInterrupt4,
- HalpHardwareInterrupt5,
- HalpHardwareInterrupt6,
- HalpHardwareInterrupt7,
- HalpHardwareInterrupt8,
- HalpHardwareInterrupt9,
- HalpHardwareInterrupt10,
- HalpHardwareInterrupt11,
- HalpHardwareInterrupt12,
- HalpHardwareInterrupt13,
- HalpHardwareInterrupt14,
- HalpHardwareInterrupt15
-};
-
-/* Handlers for pending software interrupts when we already have a trap frame*/
-PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY SWInterruptHandlerTable2[3] =
-{
- (PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)KiUnexpectedInterrupt,
- HalpApcInterrupt2ndEntry,
- HalpDispatchInterrupt2ndEntry
-};
-
-LONG HalpEisaELCR;
-
-/* FUNCTIONS ******************************************************************/
-
-VOID
-NTAPI
-HalpInitializePICs(IN BOOLEAN EnableInterrupts)
-{
- ULONG EFlags;
- I8259_ICW1 Icw1;
- I8259_ICW2 Icw2;
- I8259_ICW3 Icw3;
- I8259_ICW4 Icw4;
- EISA_ELCR Elcr;
- ULONG i, j;
-
- /* Save EFlags and disable interrupts */
- EFlags = __readeflags();
- _disable();
-
- /* Initialize ICW1 for master, interval 8, edge-triggered mode with ICW4 */
- Icw1.NeedIcw4 = TRUE;
- Icw1.InterruptMode = EdgeTriggered;
- Icw1.OperatingMode = Cascade;
- Icw1.Interval = Interval8;
- Icw1.Init = TRUE;
- Icw1.InterruptVectorAddress = 0; /* This is only used in MCS80/85 mode */
- __outbyte(PIC1_CONTROL_PORT, Icw1.Bits);
-
- /* Set interrupt vector base */
- Icw2.Bits = PRIMARY_VECTOR_BASE;
- __outbyte(PIC1_DATA_PORT, Icw2.Bits);
-
- /* Connect slave to IRQ 2 */
- Icw3.Bits = 0;
- Icw3.SlaveIrq2 = TRUE;
- __outbyte(PIC1_DATA_PORT, Icw3.Bits);
-
- /* Enable 8086 mode, non-automatic EOI, non-buffered mode, non special fully nested mode */
- Icw4.Reserved = 0;
- Icw4.SystemMode = New8086Mode;
- Icw4.EoiMode = NormalEoi;
- Icw4.BufferedMode = NonBuffered;
- Icw4.SpecialFullyNestedMode = FALSE;
- __outbyte(PIC1_DATA_PORT, Icw4.Bits);
-
- /* Mask all interrupts */
- __outbyte(PIC1_DATA_PORT, 0xFF);
-
- /* Initialize ICW1 for master, interval 8, edge-triggered mode with ICW4 */
- Icw1.NeedIcw4 = TRUE;
- Icw1.InterruptMode = EdgeTriggered;
- Icw1.OperatingMode = Cascade;
- Icw1.Interval = Interval8;
- Icw1.Init = TRUE;
- Icw1.InterruptVectorAddress = 0; /* This is only used in MCS80/85 mode */
- __outbyte(PIC2_CONTROL_PORT, Icw1.Bits);
-
- /* Set interrupt vector base */
- Icw2.Bits = PRIMARY_VECTOR_BASE + 8;
- __outbyte(PIC2_DATA_PORT, Icw2.Bits);
-
- /* Slave ID */
- Icw3.Bits = 0;
- Icw3.SlaveId = 2;
- __outbyte(PIC2_DATA_PORT, Icw3.Bits);
-
- /* Enable 8086 mode, non-automatic EOI, non-buffered mode, non special fully nested mode */
- Icw4.Reserved = 0;
- Icw4.SystemMode = New8086Mode;
- Icw4.EoiMode = NormalEoi;
- Icw4.BufferedMode = NonBuffered;
- Icw4.SpecialFullyNestedMode = FALSE;
- __outbyte(PIC2_DATA_PORT, Icw4.Bits);
-
- /* Mask all interrupts */
- __outbyte(PIC2_DATA_PORT, 0xFF);
-
- /* Read EISA Edge/Level Register for master and slave */
- Elcr.Bits = (__inbyte(EISA_ELCR_SLAVE) << 8) | __inbyte(EISA_ELCR_MASTER);
-
- /* IRQs 0, 1, 2, 8, and 13 are system-reserved and must be edge */
- if (!(Elcr.Master.Irq0Level) && !(Elcr.Master.Irq1Level) && !(Elcr.Master.Irq2Level) &&
- !(Elcr.Slave.Irq8Level) && !(Elcr.Slave.Irq13Level))
- {
- /* ELCR is as it's supposed to be, save it */
- HalpEisaELCR = Elcr.Bits;
-
- /* Scan for level interrupts */
- for (i = 1, j = 0; j < 16; i <<= 1, j++)
- {
- if (HalpEisaELCR & i)
- {
- /* Switch handler to level */
- SWInterruptHandlerTable[j + 4] = HalpHardwareInterruptLevel;
-
- /* Switch dismiss to level */
- HalpSpecialDismissTable[j] = HalpSpecialDismissLevelTable[j];
- }
- }
- }
-
- /* Restore interrupt state */
- if (EnableInterrupts) EFlags |= EFLAGS_INTERRUPT_MASK;
- __writeeflags(EFlags);
-}
-
-/* IRQL MANAGEMENT ************************************************************/
-
-/*
- * @implemented
- */
-KIRQL
-NTAPI
-KeGetCurrentIrql(VOID)
-{
- /* Return the IRQL */
- return KeGetPcr()->Irql;
-}
-
-/*
- * @implemented
- */
-KIRQL
-NTAPI
-KeRaiseIrqlToDpcLevel(VOID)
-{
- PKPCR Pcr = KeGetPcr();
- KIRQL CurrentIrql;
-
- /* Save and update IRQL */
- CurrentIrql = Pcr->Irql;
- Pcr->Irql = DISPATCH_LEVEL;
-
-#ifdef IRQL_DEBUG
- /* Validate correct raise */
- if (CurrentIrql > DISPATCH_LEVEL) KeBugCheck(IRQL_NOT_GREATER_OR_EQUAL);
-#endif
-
- /* Return the previous value */
- return CurrentIrql;
-}
-
-/*
- * @implemented
- */
-KIRQL
-NTAPI
-KeRaiseIrqlToSynchLevel(VOID)
-{
- PKPCR Pcr = KeGetPcr();
- KIRQL CurrentIrql;
-
- /* Save and update IRQL */
- CurrentIrql = Pcr->Irql;
- Pcr->Irql = SYNCH_LEVEL;
-
-#ifdef IRQL_DEBUG
- /* Validate correct raise */
- if (CurrentIrql > SYNCH_LEVEL)
- {
- /* Crash system */
- KeBugCheckEx(IRQL_NOT_GREATER_OR_EQUAL,
- CurrentIrql,
- SYNCH_LEVEL,
- 0,
- 1);
- }
-#endif
-
- /* Return the previous value */
- return CurrentIrql;
-}
-
-/*
- * @implemented
- */
-KIRQL
-FASTCALL
-KfRaiseIrql(IN KIRQL NewIrql)
-{
- PKPCR Pcr = KeGetPcr();
- KIRQL CurrentIrql;
-
- /* Read current IRQL */
- CurrentIrql = Pcr->Irql;
-
-#ifdef IRQL_DEBUG
- /* Validate correct raise */
- if (CurrentIrql > NewIrql)
- {
- /* Crash system */
- Pcr->Irql = PASSIVE_LEVEL;
- KeBugCheck(IRQL_NOT_GREATER_OR_EQUAL);
- }
-#endif
-
- /* Set new IRQL */
- Pcr->Irql = NewIrql;
-
- /* Return old IRQL */
- return CurrentIrql;
-}
-
-
-/*
- * @implemented
- */
-VOID
-FASTCALL
-KfLowerIrql(IN KIRQL OldIrql)
-{
- ULONG EFlags;
- ULONG PendingIrql, PendingIrqlMask;
- PKPCR Pcr = KeGetPcr();
- PIC_MASK Mask;
-
-#ifdef IRQL_DEBUG
- /* Validate correct lower */
- if (OldIrql > Pcr->Irql)
- {
- /* Crash system */
- Pcr->Irql = HIGH_LEVEL;
- KeBugCheck(IRQL_NOT_LESS_OR_EQUAL);
- }
-#endif
-
- /* Save EFlags and disable interrupts */
- EFlags = __readeflags();
- _disable();
-
- /* Set old IRQL */
- Pcr->Irql = OldIrql;
-
- /* Check for pending software interrupts and compare with current IRQL */
- PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
- if (PendingIrqlMask)
- {
- /* Check if pending IRQL affects hardware state */
- BitScanReverse(&PendingIrql, PendingIrqlMask);
- if (PendingIrql > DISPATCH_LEVEL)
- {
- /* Set new PIC mask */
- Mask.Both = Pcr->IDR;
- __outbyte(PIC1_DATA_PORT, Mask.Master);
- __outbyte(PIC2_DATA_PORT, Mask.Slave);
-
- /* Clear IRR bit */
- Pcr->IRR ^= (1 << PendingIrql);
- }
-
- /* Now handle pending interrupt */
- SWInterruptHandlerTable[PendingIrql]();
- }
-
- /* Restore interrupt state */
- __writeeflags(EFlags);
-}
-
-/* SOFTWARE INTERRUPTS ********************************************************/
-
-/*
- * @implemented
- */
-VOID
-FASTCALL
-HalRequestSoftwareInterrupt(IN KIRQL Irql)
-{
- ULONG EFlags;
- PKPCR Pcr = KeGetPcr();
- KIRQL PendingIrql;
-
- /* Save EFlags and disable interrupts */
- EFlags = __readeflags();
- _disable();
-
- /* Mask out the requested bit */
- Pcr->IRR |= (1 << Irql);
-
- /* Check for pending software interrupts and compare with current IRQL */
- PendingIrql = SWInterruptLookUpTable[Pcr->IRR & 3];
- if (PendingIrql > Pcr->Irql) SWInterruptHandlerTable[PendingIrql]();
-
- /* Restore interrupt state */
- __writeeflags(EFlags);
-}
-
-/*
- * @implemented
- */
-VOID
-FASTCALL
-HalClearSoftwareInterrupt(IN KIRQL Irql)
-{
- /* Mask out the requested bit */
- KeGetPcr()->IRR &= ~(1 << Irql);
-}
-
-VOID
-NTAPI
-HalpEndSoftwareInterrupt(IN KIRQL OldIrql,
- IN PKTRAP_FRAME TrapFrame)
-{
- ULONG PendingIrql, PendingIrqlMask, PendingIrqMask;
- PKPCR Pcr = KeGetPcr();
- PIC_MASK Mask;
-
- /* Set old IRQL */
- Pcr->Irql = OldIrql;
-
- /* Loop checking for pending interrupts */
- while (TRUE)
- {
- /* Check for pending software interrupts and compare with current IRQL */
- PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
- if (!PendingIrqlMask) return;
-
- /* Check for in-service delayed interrupt */
- if (Pcr->IrrActive & 0xFFFFFFF0) return;
-
- /* Check if pending IRQL affects hardware state */
- BitScanReverse(&PendingIrql, PendingIrqlMask);
- if (PendingIrql > DISPATCH_LEVEL)
- {
- /* Set new PIC mask */
- Mask.Both = Pcr->IDR;
- __outbyte(PIC1_DATA_PORT, Mask.Master);
- __outbyte(PIC2_DATA_PORT, Mask.Slave);
-
- /* Set active bit otherwise, and clear it from IRR */
- PendingIrqMask = (1 << PendingIrql);
- Pcr->IrrActive |= PendingIrqMask;
- Pcr->IRR ^= PendingIrqMask;
-
- /* Handle delayed hardware interrupt */
- SWInterruptHandlerTable[PendingIrql]();
-
- /* Handling complete */
- Pcr->IrrActive ^= PendingIrqMask;
- }
- else
- {
- /* No need to loop checking for hardware interrupts */
- SWInterruptHandlerTable2[PendingIrql](TrapFrame);
- }
- }
-}
-
-/* EDGE INTERRUPT DISMISSAL FUNCTIONS *****************************************/
-
-BOOLEAN
-FORCEINLINE
-_HalpDismissIrqGeneric(IN KIRQL Irql,
- IN ULONG Irq,
- OUT PKIRQL OldIrql)
-{
- PIC_MASK Mask;
- KIRQL CurrentIrql;
- I8259_OCW2 Ocw2;
- PKPCR Pcr = KeGetPcr();
-
- /* First save current IRQL and compare it to the requested one */
- CurrentIrql = Pcr->Irql;
-
- /* Check if this interrupt is really allowed to happen */
- if (Irql > CurrentIrql)
- {
- /* Set the new IRQL and return the current one */
- Pcr->Irql = Irql;
- *OldIrql = CurrentIrql;
-
- /* Prepare OCW2 for EOI */
- Ocw2.Bits = 0;
- Ocw2.EoiMode = SpecificEoi;
-
- /* Check which PIC needs the EOI */
- if (Irq > 8)
- {
- /* Send the EOI for the IRQ */
- __outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | (Irq - 8));
-
- /* Send the EOI for IRQ2 on the master because this was cascaded */
- __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | 2);
- }
- else
- {
- /* Send the EOI for the IRQ */
- __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | Irq);
- }
-
- /* Enable interrupts and return success */
- _enable();
- return TRUE;
- }
-
- /* Update the IRR so that we deliver this interrupt when the IRQL is proper */
- Pcr->IRR |= (1 << (Irq + 4));
-
- /* Set new PIC mask to real IRQL level, since the optimization is lost now */
- Mask.Both = KiI8259MaskTable[CurrentIrql] | Pcr->IDR;
- __outbyte(PIC1_DATA_PORT, Mask.Master);
- __outbyte(PIC2_DATA_PORT, Mask.Slave);
-
- /* Now lie and say this was spurious */
- return FALSE;
-}
-
-BOOLEAN
-__attribute__((regparm(3)))
-HalpDismissIrqGeneric(IN KIRQL Irql,
- IN ULONG Irq,
- OUT PKIRQL OldIrql)
-{
- /* Run the inline code */
- return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
-}
-
-BOOLEAN
-__attribute__((regparm(3)))
-HalpDismissIrq15(IN KIRQL Irql,
- IN ULONG Irq,
- OUT PKIRQL OldIrql)
-{
- I8259_OCW3 Ocw3;
- I8259_OCW2 Ocw2;
- I8259_ISR Isr;
-
- /* Request the ISR */
- Ocw3.Bits = 0;
- Ocw3.Sbo = 1; /* This encodes an OCW3 vs. an OCW2 */
- Ocw3.ReadRequest = ReadIsr;
- __outbyte(PIC2_CONTROL_PORT, Ocw3.Bits);
-
- /* Read the ISR */
- Isr.Bits = __inbyte(PIC2_CONTROL_PORT);
-
- /* Is IRQ15 really active (this is IR7) */
- if (Isr.Irq7 == FALSE)
- {
- /* It isn't, so we have to EOI IRQ2 because this was cascaded */
- Ocw2.Bits = 0;
- Ocw2.EoiMode = SpecificEoi;
- __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | 2);
-
- /* And now fail since this was spurious */
- return FALSE;
- }
-
- /* Do normal interrupt dismiss */
- return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
-}
-
-
-BOOLEAN
-__attribute__((regparm(3)))
-HalpDismissIrq13(IN KIRQL Irql,
- IN ULONG Irq,
- OUT PKIRQL OldIrql)
-{
- /* Clear the FPU busy latch */
- __outbyte(0xF0, 0);
-
- /* Do normal interrupt dismiss */
- return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
-}
-
-BOOLEAN
-__attribute__((regparm(3)))
-HalpDismissIrq07(IN KIRQL Irql,
- IN ULONG Irq,
- OUT PKIRQL OldIrql)
-{
- I8259_OCW3 Ocw3;
- I8259_ISR Isr;
-
- /* Request the ISR */
- Ocw3.Bits = 0;
- Ocw3.Sbo = 1;
- Ocw3.ReadRequest = ReadIsr;
- __outbyte(PIC1_CONTROL_PORT, Ocw3.Bits);
-
- /* Read the ISR */
- Isr.Bits = __inbyte(PIC1_CONTROL_PORT);
-
- /* Is IRQ 7 really active? If it isn't, this is spurious so fail */
- if (Isr.Irq7 == FALSE) return FALSE;
-
- /* Do normal interrupt dismiss */
- return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
-}
-
-/* LEVEL INTERRUPT DISMISSAL FUNCTIONS ****************************************/
-
-BOOLEAN
-FORCEINLINE
-_HalpDismissIrqLevel(IN KIRQL Irql,
- IN ULONG Irq,
- OUT PKIRQL OldIrql)
-{
- PIC_MASK Mask;
- KIRQL CurrentIrql;
- I8259_OCW2 Ocw2;
- PKPCR Pcr = KeGetPcr();
-
- /* Update the PIC */
- Mask.Both = KiI8259MaskTable[Irql] | Pcr->IDR;
- __outbyte(PIC1_DATA_PORT, Mask.Master);
- __outbyte(PIC2_DATA_PORT, Mask.Slave);
-
- /* Update the IRR so that we clear this interrupt when the IRQL is proper */
- Pcr->IRR |= (1 << (Irq + 4));
-
- /* Save current IRQL */
- CurrentIrql = Pcr->Irql;
-
- /* Prepare OCW2 for EOI */
- Ocw2.Bits = 0;
- Ocw2.EoiMode = SpecificEoi;
-
- /* Check which PIC needs the EOI */
- if (Irq > 8)
- {
- /* Send the EOI for the IRQ */
- __outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | (Irq - 8));
-
- /* Send the EOI for IRQ2 on the master because this was cascaded */
- __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | 2);
- }
- else
- {
- /* Send the EOI for the IRQ */
- __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | Irq);
- }
-
- /* Check if this interrupt should be allowed to happen */
- if (Irql > CurrentIrql)
- {
- /* Set the new IRQL and return the current one */
- Pcr->Irql = Irql;
- *OldIrql = CurrentIrql;
-
- /* Enable interrupts and return success */
- _enable();
- return TRUE;
- }
-
- /* Now lie and say this was spurious */
- return FALSE;
-}
-
-BOOLEAN
-__attribute__((regparm(3)))
-HalpDismissIrqLevel(IN KIRQL Irql,
- IN ULONG Irq,
- OUT PKIRQL OldIrql)
-{
- /* Run the inline code */
- return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
-}
-
-BOOLEAN
-__attribute__((regparm(3)))
-HalpDismissIrq15Level(IN KIRQL Irql,
- IN ULONG Irq,
- OUT PKIRQL OldIrql)
-{
- I8259_OCW3 Ocw3;
- I8259_OCW2 Ocw2;
- I8259_ISR Isr;
-
- /* Request the ISR */
- Ocw3.Bits = 0;
- Ocw3.Sbo = 1; /* This encodes an OCW3 vs. an OCW2 */
- Ocw3.ReadRequest = ReadIsr;
- __outbyte(PIC2_CONTROL_PORT, Ocw3.Bits);
-
- /* Read the ISR */
- Isr.Bits = __inbyte(PIC2_CONTROL_PORT);
-
- /* Is IRQ15 really active (this is IR7) */
- if (Isr.Irq7 == FALSE)
- {
- /* It isn't, so we have to EOI IRQ2 because this was cascaded */
- Ocw2.Bits = 0;
- Ocw2.EoiMode = SpecificEoi;
- __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | 2);
-
- /* And now fail since this was spurious */
- return FALSE;
- }
-
- /* Do normal interrupt dismiss */
- return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
-}
-
-BOOLEAN
-__attribute__((regparm(3)))
-HalpDismissIrq13Level(IN KIRQL Irql,
- IN ULONG Irq,
- OUT PKIRQL OldIrql)
-{
- /* Clear the FPU busy latch */
- __outbyte(0xF0, 0);
-
- /* Do normal interrupt dismiss */
- return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
-}
-
-BOOLEAN
-__attribute__((regparm(3)))
-HalpDismissIrq07Level(IN KIRQL Irql,
- IN ULONG Irq,
- OUT PKIRQL OldIrql)
-{
- I8259_OCW3 Ocw3;
- I8259_ISR Isr;
-
- /* Request the ISR */
- Ocw3.Bits = 0;
- Ocw3.Sbo = 1;
- Ocw3.ReadRequest = ReadIsr;
- __outbyte(PIC1_CONTROL_PORT, Ocw3.Bits);
-
- /* Read the ISR */
- Isr.Bits = __inbyte(PIC1_CONTROL_PORT);
-
- /* Is IRQ 7 really active? If it isn't, this is spurious so fail */
- if (Isr.Irq7 == FALSE) return FALSE;
-
- /* Do normal interrupt dismiss */
- return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
-}
-
-VOID
-HalpHardwareInterruptLevel(VOID)
-{
- PKPCR Pcr = KeGetPcr();
- ULONG PendingIrqlMask, PendingIrql;
-
- /* Check for pending software interrupts and compare with current IRQL */
- PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[Pcr->Irql];
- if (PendingIrqlMask)
- {
- /* Check for in-service delayed interrupt */
- if (Pcr->IrrActive & 0xFFFFFFF0) return;
-
- /* Check if pending IRQL affects hardware state */
- BitScanReverse(&PendingIrql, PendingIrqlMask);
-
- /* Clear IRR bit */
- Pcr->IRR ^= (1 << PendingIrql);
-
- /* Now handle pending interrupt */
- SWInterruptHandlerTable[PendingIrql]();
- }
-}
-
-/* SYSTEM INTERRUPTS **********************************************************/
-
-/*
- * @implemented
- */
-BOOLEAN
-NTAPI
-HalEnableSystemInterrupt(IN UCHAR Vector,
- IN KIRQL Irql,
- IN KINTERRUPT_MODE InterruptMode)
-{
- ULONG Irq;
- PKPCR Pcr = KeGetPcr();
- PIC_MASK PicMask;
-
- /* Validate the IRQ */
- Irq = Vector - PRIMARY_VECTOR_BASE;
- if (Irq >= CLOCK2_LEVEL) return FALSE;
-
- /* Check for level interrupt */
- if (InterruptMode == LevelSensitive)
- {
- /* Switch handler to level */
- SWInterruptHandlerTable[Irq + 4] = HalpHardwareInterruptLevel;
-
- /* Switch dismiss to level */
- HalpSpecialDismissTable[Irq] = HalpSpecialDismissLevelTable[Irq];
- }
-
- /* Disable interrupts */
- _disable();
-
- /* Update software IDR */
- Pcr->IDR &= ~(1 << Irq);
-
- /* Set new PIC mask */
- PicMask.Both = KiI8259MaskTable[Pcr->Irql] | Pcr->IDR;
- __outbyte(PIC1_DATA_PORT, PicMask.Master);
- __outbyte(PIC2_DATA_PORT, PicMask.Slave);
-
- /* Enable interrupts and exit */
- _enable();
- return TRUE;
-}
-
-/*
- * @implemented
- */
-VOID
-NTAPI
-HalDisableSystemInterrupt(IN UCHAR Vector,
- IN KIRQL Irql)
-{
- ULONG IrqMask;
- PIC_MASK PicMask;
-
- /* Compute new combined IRQ mask */
- IrqMask = 1 << (Vector - PRIMARY_VECTOR_BASE);
-
- /* Disable interrupts */
- _disable();
-
- /* Update software IDR */
- KeGetPcr()->IDR |= IrqMask;
-
- /* Read current interrupt mask */
- PicMask.Master = __inbyte(PIC1_DATA_PORT);
- PicMask.Slave = __inbyte(PIC2_DATA_PORT);
-
- /* Add the new disabled interrupt */
- PicMask.Both |= IrqMask;
-
- /* Write new interrupt mask */
- __outbyte(PIC1_DATA_PORT, PicMask.Master);
- __outbyte(PIC2_DATA_PORT, PicMask.Slave);
-
- /* Bring interrupts back */
- _enable();
-}
-
-/*
- * @implemented
- */
-BOOLEAN
-NTAPI
-HalBeginSystemInterrupt(IN KIRQL Irql,
- IN UCHAR Vector,
- OUT PKIRQL OldIrql)
-{
- ULONG Irq;
-
- /* Get the IRQ and call the proper routine to handle it */
- Irq = Vector - PRIMARY_VECTOR_BASE;
- return HalpSpecialDismissTable[Irq](Irql, Irq, OldIrql);
-}
-
-/*
- * @implemented
- */
-VOID
-NTAPI
-HalEndSystemInterrupt(IN KIRQL OldIrql,
- IN PKTRAP_FRAME TrapFrame)
-{
- ULONG PendingIrql, PendingIrqlMask, PendingIrqMask;
- PKPCR Pcr = KeGetPcr();
- PIC_MASK Mask;
-
- /* Set old IRQL */
- Pcr->Irql = OldIrql;
-
- /* Check for pending software interrupts and compare with current IRQL */
- PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
- if (PendingIrqlMask)
- {
- /* Check for in-service delayed interrupt */
- if (Pcr->IrrActive & 0xFFFFFFF0) return;
-
- /* Loop checking for pending interrupts */
- while (TRUE)
- {
- /* Check if pending IRQL affects hardware state */
- BitScanReverse(&PendingIrql, PendingIrqlMask);
- if (PendingIrql > DISPATCH_LEVEL)
- {
- /* Set new PIC mask */
- Mask.Both = Pcr->IDR;
- __outbyte(PIC1_DATA_PORT, Mask.Master);
- __outbyte(PIC2_DATA_PORT, Mask.Slave);
-
- /* Now check if this specific interrupt is already in-service */
- PendingIrqMask = (1 << PendingIrql);
- if (Pcr->IrrActive & PendingIrqMask) return;
-
- /* Set active bit otherwise, and clear it from IRR */
- Pcr->IrrActive |= PendingIrqMask;
- Pcr->IRR ^= PendingIrqMask;
-
- /* Handle delayed hardware interrupt */
- SWInterruptHandlerTable[PendingIrql]();
-
- /* Handling complete */
- Pcr->IrrActive ^= PendingIrqMask;
-
- /* Check if there's still interrupts pending */
- PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[Pcr->Irql];
- if (!PendingIrqlMask) break;
- }
- else
- {
- /* Now handle pending software interrupt */
- SWInterruptHandlerTable2[PendingIrql](TrapFrame);
- }
- }
- }
-}
-
-/* SOFTWARE INTERRUPT TRAPS ***************************************************/
-
-VOID
-FORCEINLINE
-DECLSPEC_NORETURN
-_HalpApcInterruptHandler(IN PKTRAP_FRAME TrapFrame)
-{
- KIRQL CurrentIrql;
- PKPCR Pcr = KeGetPcr();
-
- /* Save the current IRQL and update it */
- CurrentIrql = Pcr->Irql;
- Pcr->Irql = APC_LEVEL;
-
- /* Remove DPC from IRR */
- Pcr->IRR &= ~(1 << APC_LEVEL);
-
- /* Enable interrupts and call the kernel's APC interrupt handler */
- _enable();
- KiDeliverApc(((KiUserTrap(TrapFrame)) || (TrapFrame->EFlags & EFLAGS_V86_MASK)) ?
- UserMode : KernelMode,
- NULL,
- TrapFrame);
-
- /* Disable interrupts and end the interrupt */
- _disable();
- HalpEndSoftwareInterrupt(CurrentIrql, TrapFrame);
-
- /* Exit the interrupt */
- KiEoiHelper(TrapFrame);
-}
-
-VOID
-FASTCALL
-DECLSPEC_NORETURN
-HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame)
-{
- /* Do the work */
- _HalpApcInterruptHandler(TrapFrame);
-}
-
-VOID
-FASTCALL
-DECLSPEC_NORETURN
-HalpApcInterruptHandler(IN PKTRAP_FRAME TrapFrame)
-{
- /* Set up a fake INT Stack */
- TrapFrame->EFlags = __readeflags();
- TrapFrame->SegCs = KGDT_R0_CODE;
- TrapFrame->Eip = TrapFrame->Eax;
-
- /* Build the trap frame */
- KiEnterInterruptTrap(TrapFrame);
-
- /* Do the work */
- _HalpApcInterruptHandler(TrapFrame);
-}
-
-KIRQL
-FORCEINLINE
-_HalpDispatchInterruptHandler(VOID)
-{
- KIRQL CurrentIrql;
- PKPCR Pcr = KeGetPcr();
-
- /* Save the current IRQL and update it */
- CurrentIrql = Pcr->Irql;
- Pcr->Irql = DISPATCH_LEVEL;
-
- /* Remove DPC from IRR */
- Pcr->IRR &= ~(1 << DISPATCH_LEVEL);
-
- /* Enable interrupts and call the kernel's DPC interrupt handler */
- _enable();
- KiDispatchInterrupt();
- _disable();
-
- /* Return IRQL */
- return CurrentIrql;
-}
-
-VOID
-FASTCALL
-DECLSPEC_NORETURN
-HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame)
-{
- KIRQL CurrentIrql;
-
- /* Do the work */
- CurrentIrql = _HalpDispatchInterruptHandler();
-
- /* End the interrupt */
- HalpEndSoftwareInterrupt(CurrentIrql, TrapFrame);
-
- /* Exit the interrupt */
- KiEoiHelper(TrapFrame);
-}
-
-VOID
-HalpDispatchInterrupt2(VOID)
-{
- ULONG PendingIrqlMask, PendingIrql;
- KIRQL OldIrql;
- PIC_MASK Mask;
- PKPCR Pcr = KeGetPcr();
-
- /* Do the work */
- OldIrql = _HalpDispatchInterruptHandler();
-
- /* Restore IRQL */
- Pcr->Irql = OldIrql;
-
- /* Check for pending software interrupts and compare with current IRQL */
- PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
- if (PendingIrqlMask)
- {
- /* Check if pending IRQL affects hardware state */
- BitScanReverse(&PendingIrql, PendingIrqlMask);
- if (PendingIrql > DISPATCH_LEVEL)
- {
- /* Set new PIC mask */
- Mask.Both = Pcr->IDR;
- __outbyte(PIC1_DATA_PORT, Mask.Master);
- __outbyte(PIC2_DATA_PORT, Mask.Slave);
-
- /* Clear IRR bit */
- Pcr->IRR ^= (1 << PendingIrql);
- }
-
- /* Now handle pending interrupt */
- SWInterruptHandlerTable[PendingIrql]();
- }
-}
-
-#else
-
-KIRQL
-NTAPI
-KeGetCurrentIrql(VOID)
-{
- return PASSIVE_LEVEL;
-}
-
-VOID
-FASTCALL
-KfLowerIrql(
- IN KIRQL OldIrql)
-{
-}
-
-KIRQL
-FASTCALL
-KfRaiseIrql(
- IN KIRQL NewIrql)
-{
- return NewIrql;
-}
-
-#endif
Removed: trunk/reactos/hal/halx86/generic/portio.c
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/generic/portio.c?rev=46446&view=auto
==============================================================================
--- trunk/reactos/hal/halx86/generic/portio.c [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/generic/portio.c (removed)
@@ -1,121 +1,0 @@
-/*
- * PROJECT: ReactOS HAL
- * LICENSE: GPL - See COPYING in the top level directory
- * FILE: hal/halx86/generic/portio.c
- * PURPOSE: I/O Functions for access to ports
- * PROGRAMMERS: Alex Ionescu (alex.ionescu at reactos.org)
- */
-
-/* INCLUDES ******************************************************************/
-
-#include <hal.h>
-#define NDEBUG
-#include <debug.h>
-
-//
-// HAL Port to Inlined Port
-//
-#define H2I(Port) PtrToUshort(Port)
-
-/* FUNCTIONS *****************************************************************/
-
-VOID
-NTAPI
-READ_PORT_BUFFER_UCHAR(IN PUCHAR Port,
- OUT PUCHAR Buffer,
- IN ULONG Count)
-{
- __inbytestring(H2I(Port), Buffer, Count);
-}
-
-VOID
-NTAPI
-READ_PORT_BUFFER_USHORT(IN PUSHORT Port,
- OUT PUSHORT Buffer,
- IN ULONG Count)
-{
- __inwordstring(H2I(Port), Buffer, Count);
-}
-
-VOID
-NTAPI
-READ_PORT_BUFFER_ULONG(IN PULONG Port,
- OUT PULONG Buffer,
- IN ULONG Count)
-{
- __indwordstring(H2I(Port), Buffer, Count);
-}
-
-UCHAR
-NTAPI
-READ_PORT_UCHAR(IN PUCHAR Port)
-{
- return __inbyte(H2I(Port));
-}
-
-USHORT
-NTAPI
-READ_PORT_USHORT(IN PUSHORT Port)
-{
- return __inword(H2I(Port));
-}
-
-ULONG
-NTAPI
-READ_PORT_ULONG(IN PULONG Port)
-{
- return __indword(H2I(Port));
-}
-
-VOID
-NTAPI
-WRITE_PORT_BUFFER_UCHAR(IN PUCHAR Port,
- IN PUCHAR Buffer,
- IN ULONG Count)
-{
- __outbytestring(H2I(Port), Buffer, Count);
-}
-
-VOID
-NTAPI
-WRITE_PORT_BUFFER_USHORT(IN PUSHORT Port,
- IN PUSHORT Buffer,
- IN ULONG Count)
-{
- __outwordstring(H2I(Port), Buffer, Count);
-}
-
-VOID
-NTAPI
-WRITE_PORT_BUFFER_ULONG(IN PULONG Port,
- IN PULONG Buffer,
- IN ULONG Count)
-{
- __outdwordstring(H2I(Port), Buffer, Count);
-}
-
-VOID
-NTAPI
-WRITE_PORT_UCHAR(IN PUCHAR Port,
- IN UCHAR Value)
-{
- __outbyte(H2I(Port), Value);
-}
-
-VOID
-NTAPI
-WRITE_PORT_USHORT(IN PUSHORT Port,
- IN USHORT Value)
-{
- __outword(H2I(Port), Value);
-}
-
-VOID
-NTAPI
-WRITE_PORT_ULONG(IN PULONG Port,
- IN ULONG Value)
-{
- __outdword(H2I(Port), Value);
-}
-
-/* EOF */
Removed: trunk/reactos/hal/halx86/generic/processor.c
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/generic/processor.c?rev=46446&view=auto
==============================================================================
--- trunk/reactos/hal/halx86/generic/processor.c [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/generic/processor.c (removed)
@@ -1,98 +1,0 @@
-/*
- * PROJECT: ReactOS HAL
- * LICENSE: GPL - See COPYING in the top level directory
- * FILE: hal/halx86/up/processor.c
- * PURPOSE: HAL Processor Routines
- * PROGRAMMERS: Alex Ionescu (alex.ionescu at reactos.org)
- */
-
-/* INCLUDES ******************************************************************/
-
-#include <hal.h>
-#define NDEBUG
-#include <debug.h>
-
-LONG HalpActiveProcessors;
-KAFFINITY HalpDefaultInterruptAffinity;
-
-/* PRIVATE FUNCTIONS *********************************************************/
-
-VOID
-NTAPI
-HaliHaltSystem(VOID)
-{
- /* Disable interrupts and halt the CPU */
- _disable();
- __halt();
-}
-
-/* FUNCTIONS *****************************************************************/
-
-/*
- * @implemented
- */
-VOID
-NTAPI
-HalInitializeProcessor(IN ULONG ProcessorNumber,
- IN PLOADER_PARAMETER_BLOCK LoaderBlock)
-{
- /* Set default IDR and stall count */
- KeGetPcr()->IDR = 0xFFFFFFFB;
- KeGetPcr()->StallScaleFactor = INITIAL_STALL_COUNT;
-
- /* Update the interrupt affinity and processor mask */
- InterlockedBitTestAndSet(&HalpActiveProcessors, ProcessorNumber);
- InterlockedBitTestAndSet((PLONG)&HalpDefaultInterruptAffinity,
- ProcessorNumber);
-
- /* Register routines for KDCOM */
- HalpRegisterKdSupportFunctions();
-}
-
-/*
- * @implemented
- */
-BOOLEAN
-NTAPI
-HalAllProcessorsStarted(VOID)
-{
- /* Do nothing */
- return TRUE;
-}
-
-/*
- * @implemented
- */
-BOOLEAN
-NTAPI
-HalStartNextProcessor(IN PLOADER_PARAMETER_BLOCK LoaderBlock,
- IN PKPROCESSOR_STATE ProcessorState)
-{
- /* Ready to start */
- return FALSE;
-}
-
-/*
- * @implemented
- */
-VOID
-NTAPI
-HalProcessorIdle(VOID)
-{
- /* Enable interrupts and halt the processor */
- _enable();
- __halt();
-}
-
-/*
- * @implemented
- */
-VOID
-NTAPI
-HalRequestIpi(KAFFINITY TargetProcessors)
-{
- /* Not implemented on UP */
- __debugbreak();
-}
-
-/* EOF */
Removed: trunk/reactos/hal/halx86/generic/systimer.S
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/generic/systimer.S?rev=46446&view=auto
==============================================================================
--- trunk/reactos/hal/halx86/generic/systimer.S [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/generic/systimer.S (removed)
@@ -1,523 +1,0 @@
-/*
- * FILE: hal/halx86/generic/timer.S
- * COPYRIGHT: See COPYING in the top level directory
- * PURPOSE: System Timer Interrupt and Management
- * PROGRAMMER: Alex Ionescu (alex at relsoft.net)
- */
-
-/* INCLUDES ******************************************************************/
-
-#include <asm.h>
-.intel_syntax noprefix
-
-/* GLOBALS *******************************************************************/
-
-.globl _HalpPerfCounter
-_HalpLastPerfCounterLow: .long 0
-_HalpLastPerfCounterHigh: .long 0
-_HalpPerfCounter:
-_HalpPerfCounterLow: .long 0
-_HalpPerfCounterHigh: .long 0
-_HalpSystemHardwareFlags: .long 0
-
-_UnhandledMsg:
- .asciz "\n\x7\x7!!! Unhandled or Unexpected Code at line: %lx!!!\n"
-
-/* FUNCTIONS *****************************************************************/
-
-.global _HalpCalibrateStallExecution at 0
-.func HalpCalibrateStallExecution at 0
-_HalpCalibrateStallExecution at 0:
-
- /* Setup the stack frame */
- push ebp
- mov ebp, esp
- sub esp, 12
-
- /* Save EFLAGS and kill interrupts */
- pushf
- cli
-
- /* Get the current interrupt mask on the PICs */
- xor eax, eax
- in al, 0xA1
- shl eax, 8
- in al, 0x21
-
- /* Save it */
- push eax
-
- /* Now mask everything except the RTC and PIC 2 chain-interrupt */
- mov eax, ~((1 << 2) | (1 << 8))
-
- /* Program the PICs */
- out 0x21, al
- shr eax, 8
- out 0xA1, al
-
- /* Now get the IDT */
- sidt [ebp-8]
- mov ecx, [ebp-6]
-
- /* Get the IDT entry for the RTC */
- mov eax, 0x38
- shl eax, 3
- add ecx, eax
-
- /* Save the original RTC ISR */
- push [ecx]
- push [ecx+4]
- push ecx
-
- /* Now load our new handler */
- mov eax, offset OnlyOnePersonCanWriteHalCode
- mov [ecx], ax
- mov word ptr [ecx+2], KGDT_R0_CODE
- mov word ptr [ecx+4], 0x8E00
- shr eax, 16
- mov [ecx+6], ax
-
- /* Reset our counter */
- mov dword ptr [ebp-12], 0
-
- /* Acquire CMOS lock */
- call _HalpAcquireSystemHardwareSpinLock at 0
-
- /* Now initialize register A on the CMOS */
- mov ax, (0x2D << 8) | 0xA
- out 0x70, al
- jmp $+2
- mov al, ah
- out 0x71, al
- jmp $+2
-
- /* Read register B */
- mov ax, 0xB
- out 0x70, al
- jmp $+2
- in al, 0x71
- jmp $+2
-
- /* Don't touch the LastKnownGoodConfig hack */
- and al, 1
- mov ah, al
-
- /* Enable the interrupt */
- or ah, 0x42
-
- /* Now write the register B */
- mov al, 0xB
- out 0x70, al
- jmp $+2
- mov al, ah
- out 0x71, al
- jmp $+2
-
- /* Read register C */
- mov al, 0xC
- out 0x70, al
- jmp $+2
- in al, 0x71
- jmp $+2
-
- /* Read register D */
- mov al, 0xD
- out 0x70, al
- jmp $+2
- in al, 0x71
- jmp $+2
-
- /* Release CMOS lock */
- mov dword ptr [ebp-12], 0
- call _HalpReleaseCmosSpinLock at 0
-
- /* Initialize looper */
- xor eax, eax
-
- /* Align to 16 bytes */
- .align 16
-
- /* Enable interrupts! */
- sti
- jmp Looper
-
- /* Align to 16 bytes */
- .align 16
-
- /* Subtract one count */
-Looper:
- sub eax, 1
- jnz Looper
-
- /* ASSERT: If we got here, then the RTC never fired */
- call _DbgBreakPoint at 0
- jmp Looper
-
-OnlyOnePersonCanWriteHalCode:
- /*********************** THIS IS THE RTC HANDLER **************************/
-
- /* Increment the interrupt count and check if this is the first one */
- inc dword ptr [ebp-12]
- cmp dword ptr [ebp-12], 1
- jnz ComputeStall
-
- /*
- * It is the first one -- we'll ignore it, since it fires randomly!
- * Get rid of the old return address and push the new one in (our looper)
- */
- pop eax
- push offset Looper
-
- /* Acquire CMOS lock */
- call _HalpAcquireSystemHardwareSpinLock at 0
-
- /* Now initialize register A on the CMOS */
- mov ax, (0x2D << 8) | 0xA
- out 0x70, al
- jmp $+2
- mov al, ah
- out 0x71, al
- jmp $+2
-
- /* Read register B */
- mov ax, 0xB
- out 0x70, al
- jmp $+2
- in al, 0x71
- jmp $+2
-
- /* Don't touch the LastKnownGoodConfig hack */
- and al, 1
- mov ah, al
-
- /* Enable the interrupt */
- or ah, 0x42
-
- /* Now write the register B */
- mov al, 0xB
- out 0x70, al
- jmp $+2
- mov al, ah
- out 0x71, al
- jmp $+2
-
- /* Read register C */
- mov al, 0xC
- out 0x70, al
- jmp $+2
- in al, 0x71
- jmp $+2
-
- /* Read register D */
- mov al, 0xD
- out 0x70, al
- jmp $+2
- in al, 0x71
- jmp $+2
-
- /* Release CMOS lock */
- call _HalpReleaseCmosSpinLock at 0
-
- /* Dismiss the interrupt */
- mov al, 0x20
- out 0xA0, al
- mov al, 0x62
- out 0x20, al
-
- /* Reset the counter and return back to the looper */
- xor eax, eax
- iretd
-
- /******************* THIS IS THE 2ND RTC HANDLER **************************/
-ComputeStall:
-
- /* Do the calculation */
- neg eax
- xor edx, edx
- mov ecx, 125000 /* RTC fires every 125 ms */
- div ecx
-
- /* Is the remainder 0? */
- cmp edx, 0
- jz FoundFactor
-
- /* Otherwise fix-up the loop count */
- inc eax
-
-FoundFactor:
- /* Save the stall scale factor */
- mov fs:[KPCR_STALL_SCALE_FACTOR], eax
-
- /* Prepare for interrupt return */
- pop eax
- push offset AndItsNotYou
- mov eax, 0x13
-
- /* Acquire CMOS lock */
- call _HalpAcquireSystemHardwareSpinLock at 0
-
- /* Now initialize register A on the CMOS */
- mov ax, (0x2D << 8) | 0xA
- out 0x70, al
- jmp $+2
- mov al, ah
- out 0x71, al
- jmp $+2
-
- /* Read register B */
- mov ax, 0xB
- out 0x70, al
- jmp $+2
- in al, 0x71
- jmp $+2
-
- /* Don't touch the LastKnownGoodConfig hack */
- and al, 1
- mov ah, al
-
- /* Disable the interrupt */
- or ah, 0x2
-
- /* Now write the register B */
- mov al, 0xB
- out 0x70, al
- jmp $+2
- mov al, ah
- out 0x71, al
- jmp $+2
-
- /* Read register C */
- mov al, 0xC
- out 0x70, al
- jmp $+2
- in al, 0x71
- jmp $+2
-
- /* Release CMOS lock */
- call _HalpReleaseCmosSpinLock at 0
-
- /* Dismiss the interrupt */
- mov al, 0x20
- out 0xA0, al
- mov al, 0x62
- out 0x20, al
-
- /* Disable interrupts on return */
- and word ptr [esp+8], ~EFLAGS_INTERRUPT_MASK
- iretd
-
- /************************* WE ARE BACK FROM RTC ***************************/
-AndItsNotYou:
-
- /* Restore the IDT */
- pop ecx
- pop [ecx+4]
- pop [ecx]
-
- /* Restore the mask */
- pop eax
- out 0x21, al
- shr eax, 8
- out 0xA1, al
-
- /* Restore EFLAGS */
- popf
-
- /* Restore stack and return */
- mov esp, ebp
- pop ebp
- ret
-.endfunc
-
-#ifndef _MINIHAL_
-.globl _KeStallExecutionProcessor at 4
-.func KeStallExecutionProcessor at 4
-_KeStallExecutionProcessor at 4:
-
- /* Get the number of microseconds required */
- mov ecx, [esp+4]
- jecxz Done
-
- /* Multiply by the stall factor */
- mov eax, fs:[KPCR_STALL_SCALE_FACTOR]
- mul ecx
-
- /* Align to 16 bytes */
- .align 16
-
- /* Jump to subtraction loop */
- jmp SubtractLoop
-
- /* Align to 16 bytes */
- .align 16
-
- /* Subtract one count */
-SubtractLoop:
- sub eax, 1
- jnz SubtractLoop
-
-Done:
- /* Return */
- ret 4
-.endfunc
-#endif
-
-.global _KeQueryPerformanceCounter at 4
-.func KeQueryPerformanceCounter at 4
-_KeQueryPerformanceCounter at 4:
-
- /* Check if we were called too early */
- cmp dword ptr _HalpCurrentRollOver, 0
- je NoCount
-
- /* Save volatiles */
- push ebx
- push esi
-
-LoopPreInt:
-
- /* Disable interrupts */
- pushf
- cli
-
-LoopPostInt:
-
- /* Get the current value */
- mov ebx, _HalpPerfCounterLow
- mov esi, _HalpPerfCounterHigh
-
- /* Read 8254 timer */
- mov al, 0
- out 0x43, al
- jmp $+2
- in al, 0x40
- jmp $+2
- movzx ecx, al
- in al, 0x40
- mov ch, al
-
- /* Enable interrupts and do a short wait */
- popf
- nop
- jmp $+2
-
- /* Disable them again */
- pushf
- cli
-
- /* Get the counter value again */
- mov eax, _HalpPerfCounterLow
- mov edx, _HalpPerfCounterHigh
-
- /* Check if someone updated the counter */
- cmp eax, ebx
- jnz LoopPostInt
- cmp edx, esi
- jnz LoopPostInt
-
- /* Check if the current 8254 value causes rollover */
- neg ecx
- add ecx, _HalpCurrentRollOver
- jnb DoRollOver
-
-SetSum:
-
- /* Calculate the sum */
- add eax, ecx
- adc edx, 0
-
- /* Check if we're above or below the last high value */
- cmp edx, _HalpLastPerfCounterHigh
- jb short BelowHigh
- jnz short BelowLow
-
- /* Check if we're above or below the last low value */
- cmp eax, _HalpLastPerfCounterLow
- jb BelowHigh
-
-BelowLow:
-
- /* Update the last value and bring back interrupts */
- mov _HalpLastPerfCounterLow, eax
- mov _HalpLastPerfCounterHigh, edx
- popf
-
- /* Check if caller wants frequency */
- cmp dword ptr [esp+12], 0
- jz ReturnNoFreq
-
- /* Save hard-coded frequency */
- mov ecx, dword ptr [esp+12]
- mov dword ptr [ecx], 1193182
- mov dword ptr [ecx+4], 0
-
-ReturnNoFreq:
-
- /* Restore volatiles */
- pop esi
- pop ebx
- ret 4
-
-NoCount:
-
- /* Return empty, called too soon */
- mov eax, 0
- mov edx, 0
- ret 4
-
-DoRollOver:
-
- /* We might have an incoming interrupt, save EFLAGS and reset rollover */
- mov esi, [esp]
- mov ecx, _HalpCurrentRollOver
- popf
-
- /* Check if interrupts were enabled and try again */
- test esi, EFLAGS_INTERRUPT_MASK
- jnz LoopPreInt
-
- /* They're not, continue where we left */
- pushf
- jmp SetSum
-
-BelowHigh:
-
- /* Get the last counter values */
- mov ebx, _HalpLastPerfCounterLow
- mov esi, _HalpLastPerfCounterHigh
-
- /* Check if the previous value was 0 and go back if yes */
- mov ecx, ebx
- or ecx, esi
- jz BelowLow
-
- /* Make sure that the count is still valid */
- sub ebx, eax
- sbb esi, edx
- jnz InvalidCount
- cmp ebx, _HalpCurrentRollOver
- jg InvalidCount
-
- /* Fixup the count with the last known value */
- sub eax, ebx
- sbb edx, esi
-
- /* We might have an incoming interrupt, save EFLAGS */
- mov ecx, [esp]
- popf
-
- /* Check if interrupts were enabled and try again */
- test ecx, EFLAGS_INTERRUPT_MASK
- jnz LoopPreInt
-
- /* They're not, continue where we left */
- pushf
- jmp BelowLow
-
-InvalidCount:
- popf
- xor eax, eax
- mov _HalpLastPerfCounterLow, eax
- mov _HalpLastPerfCounterHigh, eax
- jmp LoopPreInt
-.endfunc
Removed: trunk/reactos/hal/halx86/generic/trap.S
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/generic/trap.S?rev=46446&view=auto
==============================================================================
--- trunk/reactos/hal/halx86/generic/trap.S [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/generic/trap.S (removed)
@@ -1,45 +1,0 @@
-/*
- * FILE: ntoskrnl/ke/i386/trap.S
- * COPYRIGHT: See COPYING in the top level directory
- * PURPOSE: System Traps, Entrypoints and Exitpoints
- * PROGRAMMER: Timo Kreuzer (timo.kreuzer at reactos.org)
- * NOTE: See asmmacro.S for the shared entry/exit code.
- */
-
-/* INCLUDES ******************************************************************/
-
-#include <reactos/asm.h>
-#include <ndk/i386/asm.h>
-#include <internal/i386/asmmacro.S>
-
-.code32
-.text
-
-TRAP_ENTRY HalpTrap0D, 0
-TRAP_ENTRY HalpApcInterrupt, KI_SOFTWARE_TRAP
-TRAP_ENTRY HalpClockInterrupt, KI_PUSH_FAKE_ERROR_CODE
-TRAP_ENTRY HalpProfileInterrupt, KI_PUSH_FAKE_ERROR_CODE
-
-PUBLIC @HalpExitToV86 at 4
- at HalpExitToV86@4:
- /* Point esp to the iret frame and return */
- lea esp, [ecx + KTRAP_FRAME_EIP]
- iret
-
-/* Here starts the real mode code */
-.code16
-PUBLIC _HalpRealModeStart
-_HalpRealModeStart:
- /* INT 0x10: AH = 0 (Set video Mode), AL = 0x12 (Mode 12) */
- mov eax, HEX(12)
- int HEX(10)
-
- /* BOP */
- .byte HEX(C4), HEX(C4)
-
-/* The real mode stack */
-.align 4
-.space 2048
-_HalpRealModeEnd:
-PUBLIC _HalpRealModeEnd
-
Modified: trunk/reactos/hal/halx86/hal_generic.rbuild
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/hal_generic.rbuild?rev=46447&r1=46446&r2=46447&view=diff
==============================================================================
--- trunk/reactos/hal/halx86/hal_generic.rbuild [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/hal_generic.rbuild [iso-8859-1] Thu Mar 25 20:23:09 2010
@@ -18,24 +18,35 @@
<file>beep.c</file>
<file>bios.c</file>
<file>cmos.c</file>
+ <file>display.c</file>
<file>dma.c</file>
<file>drive.c</file>
- <file>display.c</file>
<file>halinit.c</file>
<file>misc.c</file>
- <file>portio.c</file>
<file>profil.c</file>
<file>reboot.c</file>
<file>sysinfo.c</file>
- <file>systimer.S</file>
<file>timer.c</file>
- <file>trap.S</file>
<file>usage.c</file>
+ <if property="ARCH" value="i386">
+ <directory name="i386">
+ <file>portio.c</file>
+ <file>systimer.S</file>
+ <file>trap.S</file>
+ </directory>
+ </if>
+ <if property="ARCH" value="amd64">
+ <directory name="amd64">
+ <file>x86bios.c</file>
+ <file>systimer.S</file>
+ </directory>
+ </if>
</directory>
<directory name="include">
<pch>hal.h</pch>
</directory>
</module>
+
<module name="mini_hal" type="objectlibrary">
<include>include</include>
<include base="ntoskrnl">include</include>
Modified: trunk/reactos/hal/halx86/hal_generic_up.rbuild
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/hal_generic_up.rbuild?rev=46447&r1=46446&r2=46447&view=diff
==============================================================================
--- trunk/reactos/hal/halx86/hal_generic_up.rbuild [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/hal_generic_up.rbuild [iso-8859-1] Thu Mar 25 20:23:09 2010
@@ -9,7 +9,7 @@
<directory name="generic">
<file>spinlock.c</file>
</directory>
- <directory name="generic">
+ <directory name="up">
<file>pic.c</file>
<file>processor.c</file>
</directory>
Modified: trunk/reactos/hal/halx86/halmps.rbuild
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/halmps.rbuild?rev=46447&r1=46446&r2=46447&view=diff
==============================================================================
--- trunk/reactos/hal/halx86/halmps.rbuild [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/halmps.rbuild [iso-8859-1] Thu Mar 25 20:23:09 2010
@@ -14,10 +14,13 @@
<library>ntoskrnl</library>
<library>libcntpr</library>
<directory name="mp">
- <file>mps.S</file>
- <file>mpsboot.asm</file>
- <file>mpsirql.c</file>
-
+ <if property="ARCH" value="i386">
+ <directory name="i386">
+ <file>mps.S</file>
+ <file>mpsboot.asm</file>
+ <file>mpsirql.c</file>
+ </directory>
+ </if>
</directory>
</module>
</group>
Propchange: trunk/reactos/hal/halx86/mp/amd64/
------------------------------------------------------------------------------
--- bugtraq:logregex (added)
+++ bugtraq:logregex Thu Mar 25 20:23:09 2010
@@ -1,0 +1,2 @@
+([Ii]ssue|[Bb]ug)s? #?(\d+)(,? ?#?(\d+))*(,? ?(and |or )?#?(\d+))?
+(\d+)
Propchange: trunk/reactos/hal/halx86/mp/amd64/
------------------------------------------------------------------------------
bugtraq:message = See issue #%BUGID% for more details.
Propchange: trunk/reactos/hal/halx86/mp/amd64/
------------------------------------------------------------------------------
bugtraq:url = http://www.reactos.org/bugzilla/show_bug.cgi?id=%BUGID%
Propchange: trunk/reactos/hal/halx86/mp/amd64/
------------------------------------------------------------------------------
tsvn:logminsize = 10
Propchange: trunk/reactos/hal/halx86/mp/i386/
------------------------------------------------------------------------------
--- bugtraq:logregex (added)
+++ bugtraq:logregex Thu Mar 25 20:23:09 2010
@@ -1,0 +1,2 @@
+([Ii]ssue|[Bb]ug)s? #?(\d+)(,? ?#?(\d+))*(,? ?(and |or )?#?(\d+))?
+(\d+)
Propchange: trunk/reactos/hal/halx86/mp/i386/
------------------------------------------------------------------------------
bugtraq:message = See issue #%BUGID% for more details.
Propchange: trunk/reactos/hal/halx86/mp/i386/
------------------------------------------------------------------------------
bugtraq:url = http://www.reactos.org/bugzilla/show_bug.cgi?id=%BUGID%
Propchange: trunk/reactos/hal/halx86/mp/i386/
------------------------------------------------------------------------------
tsvn:logminsize = 10
Removed: trunk/reactos/hal/halx86/mp/mps.S
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/mp/mps.S?rev=46446&view=auto
==============================================================================
--- trunk/reactos/hal/halx86/mp/mps.S [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/mp/mps.S (removed)
@@ -1,109 +1,0 @@
-/* $Id$
- *
- * COPYRIGHT: See COPYING in the top level directory
- * PROJECT: ReactOS kernel
- * FILE: hal/halx86/mp/mps.S
- * PURPOSE: Intel MultiProcessor specification support
- * PROGRAMMER: Casper S. Hornstrup (chorns at users.sourceforge.net)
- * UPDATE HISTORY:
- * Created 12/04/2001
- */
-
-/* INCLUDES ******************************************************************/
-
-#include <ndk/asm.h>
-
-/* FUNCTIONS *****************************************************************/
-
-#define BEFORE \
- cld; \
- pusha; \
- pushl %ds; \
- pushl %es; \
- pushl %fs; \
- pushl %gs; \
- movl $(KGDT_R0_DATA), %eax; \
- movl %eax, %ds; \
- movl %eax, %es; \
- movl %eax, %gs; \
- movl $(KGDT_R0_PCR), %eax; \
- movl %eax, %fs;
-
-#define AFTER \
- popl %gs; \
- popl %fs; \
- popl %es; \
- popl %ds; \
- popa;
-
-.global _MpsIpiInterrupt
-_MpsIpiInterrupt:
- /* Save registers */
- BEFORE
-
- /* Call the C handler */
- call _MpsIpiHandler
-
- /* Return to the caller */
- AFTER
- iret
-
-
-.globl _MpsErrorInterrupt
-_MpsErrorInterrupt:
- /* Save registers */
- BEFORE
-
- /* Call the C handler */
- call _MpsErrorHandler
-
- /* Return to the caller */
- AFTER
- iret
-
-
-.globl _MpsSpuriousInterrupt
-_MpsSpuriousInterrupt:
- /* Save registers */
- BEFORE
-
- /* Call the C handler */
- call _MpsSpuriousHandler
-
- /* Return to the caller */
- AFTER
- iret
-
-.global _MpsTimerInterrupt
-_MpsTimerInterrupt:
- cld
- pusha
- movl $0xef,%ebx
- pushl %ds
- pushl %es
- pushl %fs
- pushl %gs
- movl $0xceafbeef,%eax
- pushl %eax
- movl $(KGDT_R0_DATA),%eax
- movl %eax,%ds
- movl %eax,%es
- movl %eax,%gs
- movl $(KGDT_R0_PCR),%eax
- movl %eax,%fs
- pushl %esp
- pushl %ebx
- call _MpsTimerHandler
- popl %eax
- popl %eax
- popl %eax
- popl %gs
- popl %fs
- popl %es
- popl %ds
- popa
- iret
-
-
-
-/* EOF */
Removed: trunk/reactos/hal/halx86/mp/mpsboot.asm
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/mp/mpsboot.asm?rev=46446&view=auto
==============================================================================
--- trunk/reactos/hal/halx86/mp/mpsboot.asm [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/mp/mpsboot.asm (removed)
@@ -1,118 +1,0 @@
-;
-; COPYRIGHT: See COPYING in the top level directory
-; PROJECT: ReactOS kernel
-; FILE: hal/halx86/mp/mpsboot.c
-; PURPOSE: Bootstrap code for application processors
-; PROGRAMMER: Casper S. Hornstrup (chorns at users.sourceforge.net)
-; UPDATE HISTORY:
-; Created 12/04/2001
-;
-
-;
-; Memory map at this stage is:
-; 0x2000 Location of our stack
-; 0x3000 Startup code for the APs (this code)
-;
-
-;
-; Magic value to be put in EAX when multiboot.S is called as part of the
-; application processor initialization process
-;
-AP_MAGIC equ 12481020h
-
-
-X86_CR4_PAE equ 00000020h
-
-;
-; Segment selectors
-;
-%define KERNEL_CS (0x8)
-%define KERNEL_DS (0x10)
-
-section .text
-
-global _APstart
-global _APend
-
-; 16 bit code
-BITS 16
-
-_APstart:
- cli ; Just in case
-
- xor ax, ax
- mov ds, ax
- mov ss, ax
-
- mov eax, 3000h + APgdt - _APstart
- lgdt [eax]
-
- mov eax, [2004h] ; Set the page directory
- mov cr3, eax
-
- mov eax, [200ch]
- cmp eax,0
- je NoPae
-
- mov eax,cr4
- or eax,X86_CR4_PAE
- mov cr4,eax
-
-NoPae:
-
- mov eax, cr0
- or eax, 80010001h ; Turn on protected mode, paging and write protection
- mov cr0, eax
-
- db 0eah
- dw 3000h + flush - _APstart, KERNEL_CS
-
-; 32 bit code
-BITS 32
-
-flush:
- mov ax, KERNEL_DS
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
-
- ; Setup a stack for the AP
- mov eax, 2000h
- mov eax, [eax]
- mov esp, eax
-
- ; Jump to start of the kernel with AP magic in ecx
- mov ecx, AP_MAGIC
- mov eax,[2008h]
- jmp eax
-
- ; Never get here
-
-
-; Temporary GDT descriptor for the APs
-
-APgdt:
-; Limit
- dw (3*8)-1
-; Base
- dd 3000h + gdt - _APstart
-
-gdt:
- dw 0x0 ; Null descriptor
- dw 0x0
- dw 0x0
- dw 0x0
-
- dw 0xffff ; Kernel code descriptor
- dw 0x0000
- dw 0x9a00
- dw 0x00cf
-
- dw 0xffff ; Kernel data descriptor
- dw 0x0000
- dw 0x9200
- dw 0x00cf
-
-_APend:
Removed: trunk/reactos/hal/halx86/mp/mpsirql.c
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/mp/mpsirql.c?rev=46446&view=auto
==============================================================================
--- trunk/reactos/hal/halx86/mp/mpsirql.c [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/mp/mpsirql.c (removed)
@@ -1,358 +1,0 @@
-/*
- * COPYRIGHT: See COPYING in the top level directory
- * PROJECT: ReactOS kernel
- * FILE: hal/halx86/mp/mpsirql.c
- * PURPOSE: Implements IRQLs for multiprocessor systems
- * PROGRAMMERS: David Welch (welch at cwcom.net)
- * Casper S. Hornstrup (chorns at users.sourceforge.net)
- * UPDATE HISTORY:
- * 12/04/2001 CSH Created
- */
-
-/* INCLUDES *****************************************************************/
-
-#include <hal.h>
-#define NDEBUG
-#include <debug.h>
-
-/* GLOBALS ******************************************************************/
-
-
-/* FUNCTIONS ****************************************************************/
-
-#undef KeGetCurrentIrql
-KIRQL NTAPI KeGetCurrentIrql (VOID)
-/*
- * PURPOSE: Returns the current irq level
- * RETURNS: The current irq level
- */
-{
- KIRQL irql;
- ULONG Flags;
-
- Flags = __readeflags();
- _disable();
-
- irql = __readfsbyte(FIELD_OFFSET(KPCR, Irql));
- if (irql > HIGH_LEVEL)
- {
- DPRINT1 ("CurrentIrql %x\n", irql);
- ASSERT(FALSE);
- }
- if (Flags & EFLAGS_INTERRUPT_MASK)
- {
- _enable();
- }
- return irql;
-}
-
-
-#undef KeSetCurrentIrql
-VOID KeSetCurrentIrql (KIRQL NewIrql)
-/*
- * PURPOSE: Sets the current irq level without taking any action
- */
-{
- ULONG Flags;
- if (NewIrql > HIGH_LEVEL)
- {
- DPRINT1 ("NewIrql %x\n", NewIrql);
- ASSERT(FALSE);
- }
- Flags = __readeflags();
- _disable();
- __writefsbyte(FIELD_OFFSET(KPCR, Irql), NewIrql);
- if (Flags & EFLAGS_INTERRUPT_MASK)
- {
- _enable();
- }
-}
-
-VOID
-HalpLowerIrql(KIRQL NewIrql, BOOLEAN FromHalEndSystemInterrupt)
-{
- ULONG Flags;
- UCHAR DpcRequested;
- if (NewIrql >= DISPATCH_LEVEL)
- {
- KeSetCurrentIrql (NewIrql);
- APICWrite(APIC_TPR, IRQL2TPR (NewIrql) & APIC_TPR_PRI);
- return;
- }
- Flags = __readeflags();
- if (KeGetCurrentIrql() > APC_LEVEL)
- {
- KeSetCurrentIrql (DISPATCH_LEVEL);
- APICWrite(APIC_TPR, IRQL2TPR (DISPATCH_LEVEL) & APIC_TPR_PRI);
- DpcRequested = __readfsbyte(FIELD_OFFSET(KIPCR, HalReserved[HAL_DPC_REQUEST]));
- if (FromHalEndSystemInterrupt || DpcRequested)
- {
- __writefsbyte(FIELD_OFFSET(KIPCR, HalReserved[HAL_DPC_REQUEST]), 0);
- _enable();
- KiDispatchInterrupt();
- if (!(Flags & EFLAGS_INTERRUPT_MASK))
- {
- _disable();
- }
- }
- KeSetCurrentIrql (APC_LEVEL);
- }
- if (NewIrql == APC_LEVEL)
- {
- return;
- }
- if (KeGetCurrentThread () != NULL &&
- KeGetCurrentThread ()->ApcState.KernelApcPending)
- {
- _enable();
- KiDeliverApc(KernelMode, NULL, NULL);
- if (!(Flags & EFLAGS_INTERRUPT_MASK))
- {
- _disable();
- }
- }
- KeSetCurrentIrql (PASSIVE_LEVEL);
-}
-
-
-/**********************************************************************
- * NAME EXPORTED
- * KfLowerIrql
- *
- * DESCRIPTION
- * Restores the irq level on the current processor
- *
- * ARGUMENTS
- * NewIrql = Irql to lower to
- *
- * RETURN VALUE
- * None
- *
- * NOTES
- * Uses fastcall convention
- */
-VOID FASTCALL
-KfLowerIrql (KIRQL NewIrql)
-{
- KIRQL oldIrql = KeGetCurrentIrql();
- if (NewIrql > oldIrql)
- {
- DPRINT1 ("NewIrql %x CurrentIrql %x\n", NewIrql, oldIrql);
- ASSERT(FALSE);
- }
- HalpLowerIrql (NewIrql, FALSE);
-}
-
-
-/**********************************************************************
- * NAME EXPORTED
- * KfRaiseIrql
- *
- * DESCRIPTION
- * Raises the hardware priority (irql)
- *
- * ARGUMENTS
- * NewIrql = Irql to raise to
- *
- * RETURN VALUE
- * previous irq level
- *
- * NOTES
- * Uses fastcall convention
- */
-
-KIRQL FASTCALL
-KfRaiseIrql (KIRQL NewIrql)
-{
- KIRQL OldIrql;
- ULONG Flags;
-
- Flags = __readeflags();
- _disable();
-
- OldIrql = KeGetCurrentIrql ();
-
- if (NewIrql < OldIrql)
- {
- DPRINT1 ("CurrentIrql %x NewIrql %x\n", KeGetCurrentIrql (), NewIrql);
- ASSERT(FALSE);
- }
-
-
- if (NewIrql > DISPATCH_LEVEL)
- {
- APICWrite (APIC_TPR, IRQL2TPR(NewIrql) & APIC_TPR_PRI);
- }
- KeSetCurrentIrql (NewIrql);
- if (Flags & EFLAGS_INTERRUPT_MASK)
- {
- _enable();
- }
-
- return OldIrql;
-}
-
-/**********************************************************************
- * NAME EXPORTED
- * KeRaiseIrqlToDpcLevel
- *
- * DESCRIPTION
- * Raises the hardware priority (irql) to DISPATCH level
- *
- * ARGUMENTS
- * None
- *
- * RETURN VALUE
- * Previous irq level
- *
- * NOTES
- * Calls KfRaiseIrql
- */
-
-KIRQL NTAPI
-KeRaiseIrqlToDpcLevel (VOID)
-{
- return KfRaiseIrql (DISPATCH_LEVEL);
-}
-
-
-/**********************************************************************
- * NAME EXPORTED
- * KeRaiseIrqlToSynchLevel
- *
- * DESCRIPTION
- * Raises the hardware priority (irql) to CLOCK2 level
- *
- * ARGUMENTS
- * None
- *
- * RETURN VALUE
- * Previous irq level
- *
- * NOTES
- * Calls KfRaiseIrql
- */
-
-KIRQL NTAPI
-KeRaiseIrqlToSynchLevel (VOID)
-{
- return KfRaiseIrql (CLOCK2_LEVEL);
-}
-
-
-BOOLEAN NTAPI
-HalBeginSystemInterrupt (KIRQL Irql,
- UCHAR Vector,
- PKIRQL OldIrql)
-{
- ULONG Flags;
- DPRINT("Vector (0x%X) Irql (0x%X)\n", Vector, Irql);
-
- if (KeGetCurrentIrql () >= Irql)
- {
- DPRINT1("current irql %d, new irql %d\n", KeGetCurrentIrql(), Irql);
- ASSERT(FALSE);
- }
-
- Flags = __readeflags();
- if (Flags & EFLAGS_INTERRUPT_MASK)
- {
- DPRINT1("HalBeginSystemInterrupt was called with interrupt's enabled\n");
- ASSERT(FALSE);
- }
- APICWrite (APIC_TPR, IRQL2TPR (Irql) & APIC_TPR_PRI);
- *OldIrql = KeGetCurrentIrql ();
- KeSetCurrentIrql (Irql);
- return(TRUE);
-}
-
-
-VOID NTAPI
-HalEndSystemInterrupt (KIRQL Irql,
- IN PKTRAP_FRAME TrapFrame)
-/*
- * FUNCTION: Finish a system interrupt and restore the specified irq level.
- */
-{
- ULONG Flags;
- Flags = __readeflags();
-
- if (Flags & EFLAGS_INTERRUPT_MASK)
- {
- DPRINT1("HalEndSystemInterrupt was called with interrupt's enabled\n");
- ASSERT(FALSE);
- }
- APICSendEOI();
- HalpLowerIrql (Irql, TRUE);
-}
-
-VOID
-NTAPI
-HalDisableSystemInterrupt(UCHAR Vector,
- KIRQL Irql)
-{
- ULONG irq;
-
- DPRINT ("Vector (0x%X)\n", Vector);
-
- if (Vector < FIRST_DEVICE_VECTOR ||
- Vector >= FIRST_DEVICE_VECTOR + NUMBER_DEVICE_VECTORS)
- {
- DPRINT1("Not a device interrupt, vector=%x\n", Vector);
- ASSERT(FALSE);
- return;
- }
-
- irq = VECTOR2IRQ (Vector);
- IOAPICMaskIrq (irq);
-
- return;
-}
-
-
-BOOLEAN NTAPI
-HalEnableSystemInterrupt (UCHAR Vector,
- KIRQL Irql,
- KINTERRUPT_MODE InterruptMode)
-{
- ULONG irq;
-
- if (Vector < FIRST_DEVICE_VECTOR ||
- Vector >= FIRST_DEVICE_VECTOR + NUMBER_DEVICE_VECTORS)
- {
- DPRINT("Not a device interrupt\n");
- return FALSE;
- }
-
- /* FIXME: We must check if the requested and the assigned interrupt mode is the same */
-
- irq = VECTOR2IRQ (Vector);
- IOAPICUnmaskIrq (irq);
-
- return TRUE;
-}
-
-VOID FASTCALL
-HalRequestSoftwareInterrupt(IN KIRQL Request)
-{
- switch (Request)
- {
- case APC_LEVEL:
- __writefsbyte(FIELD_OFFSET(KIPCR, HalReserved[HAL_APC_REQUEST]), 1);
- break;
-
- case DISPATCH_LEVEL:
- __writefsbyte(FIELD_OFFSET(KIPCR, HalReserved[HAL_DPC_REQUEST]), 1);
- break;
-
- default:
- ASSERT(FALSE);
- }
-}
-
-VOID FASTCALL
-HalClearSoftwareInterrupt(
- IN KIRQL Request)
-{
- UNIMPLEMENTED;
-}
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